ePWM Registers
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SPNU563A–March 2018
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Enhanced Pulse Width Modulator (ePWM) Module
35.4.8.4 Digital Compare B Control Register (DCBCTL)
Figure 35-94. Digital Compare B Control Register (DCBCTL) [offset = 66h]
15 10 9 8
Reserved EVT2FRC
SYNCSEL
EVT2SRCSEL
R-0 R/W-0 R/W-0
7 4 3 2 1 0
Reserved EVT1SYNCE EVT1SOCE EVT1FRC
SYNCSEL
EVT1SRCSEL
R-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35-54. Digital Compare B Control Register (DCBCTL) Field Descriptions
Bit Field Value Description
15-10 Reserved 0 Reserved
9 EVT2FRC SYNCSEL DCBEVT2 Force Synchronization Signal Select.
0 Source Is Synchronous Signal.
1 Source Is Asynchronous Signal.
8 EVT2SRCSEL DCBEVT2 Source Signal Select.
0 Source Is DCBEVT2 Signal.
1 Source Is DCEVTFILT Signal.
7-4 Reserved 0 Reserved
3 EVT1SYNCE DCBEVT1 SYNC, Enable.
0 SYNC Generation is disabled.
1 SYNC Generation is enabled.
2 EVT1SOCE DCBEVT1 SOC, Enable.
0 SOC Generation is disabled.
1 SOC Generation is enabled.
1 EVT1FRC SYNCSEL DCBEVT1 Force Synchronization Signal Select.
0 Source Is Synchronous Signal.
1 Source Is Asynchronous Signal.
0 EVT1SRCSEL DCBEVT1 Source Signal Select.
0 Source Is DCBEVT1 Signal.
1 Source Is DCEVTFILT Signal.