Module Operation
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SPNU563A–March 2018
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Data Modification Module (DMM)
The packet consists only of data bits and no header information. It can be 8-, 16- or 32-bit wide. A variable
packet width is not supported because the DMM module will check the number of incoming bits (DMMCLK
cycles) for error detection. The DMM will write the received data to the destination once the programmed
number of bits has been received.
If the programmed word width does not correspond to the received data, the following actions will be
taken:
• If the received data is greater than the programmed width, only the configured number of bits are
transferred into the RAM buffer, the additional bits are discarded.
• If the received number of bits is smaller than the programmed width, no data will be written to the
buffer, because a new DMMSYNC signal has been received before the expected number of bits.
36.2.2 Data Port
The packet will be received in several subpackets, depending on the width of the external data bus
(DMMDATA[y:0]) and the amount of data to be transmitted. Table 36-4 illustrates the number of clock
cycles required for a complete packet.
Table 36-4. Number of Clock Cycles per Packet
Port Width/ Pins
Write Size in Bits
8 16 32 64
1 32 40 56 88
2 16 20 28 44
4 8 10 14 22
8 4 5 7 11
16 2 3 4 6
The user can program the port width in the DMMPC0 register (Section 36.3.16). This feature allows pins
that are not used for DMM functionality to be used as GIO pins. Only the pins shown in Table 36-5 can be
used for a desired port width.
Table 36-5. Pins Used for Data Communication
Port Width Pins Used
1 DMMDATA[0]
2 DMMDATA[1:0]
4 DMMDATA[3:0]
8 DMMDATA[7:0]
16 DMMDATA[15:0]
NOTE: If pins other than the ones specified in Table 36-5 are programmed as functional pins for a
desired port width, the received data will be corrupted and will not be transferred to the
deserializer.
NOTE: If DMMCLK or DMMSYNC are programmed as nonfunctional pins, functional operation will
not occur.
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