Control Registers
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SPNU563A–March 2018
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Data Modification Module (DMM)
Table 36-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued)
Bit Field Value Description
1 DEST0_ERR Destination 0 Error Interrupt Set.This disables the interrupt generation in case data should be
written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or
DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed to 0 or a reserved
value, the interrupt will still be generated, the write to the internal RAM however will not take
place.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
0 PACKET_ERR_INT Packet Error.This disables the interrupt generation in case of an error condition in the packet
reception. Please refer to Section 36.2.3for the error conditions.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
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