Texas Instruments TMS570LC4357

Per1
Per2
PerN
Per1
Per2
PerN
PCR1 PCR3
Lower
256k
L2 SRAM
Upper
256k
L2 SRAM
CPU Interconnect Subsystem Peripheral Interconnect Subsystem
CPU
FIFO1 FIFO2 FIFO3 FIFO4
RAM Trace Port
SERIALIZER
RTPENA
RTPSYNC
RTPCLK
RTPDATA[x]
RTPDATA[0]
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2156
SPNU563A–March 2018
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RAM Trace Port (RTP)
37.1.2 Block Diagram
Figure 37-1 is a block diagram of the RTP.
Figure 37-1. RAM Trace Port Module Block Diagram