RTP Control Registers
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SPNU563A–March 2018
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RAM Trace Port (RTP)
37.3.8 RTP Direct Data Mode Write Register (RTPDDMW)
The CPU has to write data to this register if the module is used in Direct Data Mode write configuration.
Figure 37-16 and Table 37-17 describe this register.
Figure 37-16. RTP Direct Data Mode Write Register (RTPDDMW) (offset = 2Ch)
31 0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 37-17. RTP Direct Data Mode Write Register (RTPDDMW) Field Descriptions
Bit Field Description
31-0 DATA This register must be written to in a Direct Data Mode write operation to store the data into FIFO1. Data written
must be right-aligned. If the FIFO is full, the reaction depends on the setting of the HOVF bit (RTPGLBCTRL).
If the bit is set, the master writing the data will be wait-stated. If the bit is cleared, previous data written to the
register will be overwritten.
Reads of this register always return 0.
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