System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.35 Privileged Peripheral Frame n MasterID Protection Register_L/H (PPS[1-7]MSTID_L/H)
Figure 2-106. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H)
(offset = 408h-43Ch)
31 16
PPSn_QUAD3_MSTID or PPSn_QUAD1_MSTID
R/WP-FFFFh
15 0
PPSn_QUAD2_MSTID or PPSn_QUAD0_MSTID
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-120. Privileged Peripheral Frame n MasterID Protection Register_L/H (PPSnMSTID_L/H)
Field Descriptions
Bit Field Value Description
31-16 PPSn_QUAD3_MSTID or
PPSn_QUAD1_MSTID
n: 1 to 7. L: quadrant0 and quadrant1. H: quadrant2 and quadrant3.
MasterID filtering for Quadrant 3 of PPS[n] or Quadrant 1 of PPS[n].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
15-0 PPSn_QUAD2_MSTID or
PPSn_QUAD0_MSTID
MasterID filtering for Quadrant 2 of PPS[n] or Quadrant 0 of PPS[n].
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
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