System and Peripheral Control Registers
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SPNU563A–March 2018
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Architecture
2.5.3.39 Peripheral Memory Frame MasterID Protection Register (PCS[0-31]MSTID)
Figure 2-110. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID)
(offset = 540h-5BCh)
31 16
PCS(2n+1)_MSTID
R/WP-FFFFh
15 0
PCS(2n)_MSTID
R/WP-FFFFh
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 2-124. Peripheral Memory Frame MasterID Protection Register (PCSnMSTID)
Field Descriptions
Bit Field Value Description
31-16 PCS(2n+1)_MSTID MasterID filtering for PCS[2n+1], where n = 0 to 31.
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
15-0 PCS(2n)_MSTID MasterID filtering for PCS[2n], where n = 0 to 31.
0 Read: The corresponding master-ID is not permitted to access the peripheral.
Write: Disable the permission of the corresponding master to access the peripheral.
1 Read: The corresponding master-ID is permitted to access the peripheral.
Write: Enable the permission of the corresponding master to access the peripheral.
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