Control of Multiplexed Inputs
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SPNU563A–March 2018
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I/O Multiplexing and Control Module (IOMM)
Table 6-2. Input Multiplexing and Control on 337ZWT Package (continued)
Address
Offset
Signal Name Default Terminal Terminal 1 Input
Multiplex Control
Alternate Terminal Terminal 2 Input
Multiplex Control
280h N2HET1[17] A13 PINMMR92[0] F3 PINMMR92[1]
N2HET1[19] B13 PINMMR92[8] G3 PINMMR92[9]
N2HET1[21] H4 PINMMR92[16] J3 PINMMR92[17]
N2HET1[23] J4 PINMMR92[24] G19 PINMMR92[25]
284h N2HET1[25] M3 PINMMR93[0] V5 PINMMR93[1]
N2HET1[27] A9 PINMMR93[8] B2 PINMMR93[9]
N2HET1[29] A3 PINMMR93[16] C3 PINMMR93[17]
N2HET1[31] J17 PINMMR93[24] W9 PINMMR93[25]
288h N2HET2[00] D6 PINMMR94[0] C1 PINMMR94[1]
N2HET2[01] D8 PINMMR94[8] D4 PINMMR94[9]
N2HET2[02] D7 PINMMR94[16] E1 PINMMR94[17]
N2HET2[03] E2 PINMMR94[24] D5 PINMMR94[25]
28Ch N2HET2[04] D13 PINMMR95[0] H3 PINMMR95[1]
N2HET2[05] D12 PINMMR95[8] D16 PINMMR95[9]
N2HET2[06] D11 PINMMR95[16] M1 PINMMR95[17]
N2HET2[07] N3 PINMMR95[24] N17 PINMMR95[25]
290h N2HET2[08] K16 PINMMR96[0] V2 PINMMR96[1]
N2HET2[09] L16 PINMMR96[8] K17 PINMMR96[9]
N2HET2[10] M16 PINMMR96[16] U1 PINMMR96[17]
N2HET2[11] N16 PINMMR96[24] C4 PINMMR96[25]
294h N2HET2[12] D3 PINMMR97[0] V6 PINMMR97[1]
N2HET2[13] D2 PINMMR97[8] C5 PINMMR97[9]
N2HET2[14] D1 PINMMR97[16] T1 PINMMR97[17]
N2HET2[15] K4 PINMMR97[24] C6 PINMMR97[25]
298h N2HET2[16] L4 PINMMR98[0] V7 PINMMR98[1]
N2HET2[18] N4 PINMMR98[8] E3 PINMMR98[9]
N2HET2[20] T5 PINMMR98[16] N2 PINMMR98[17]
N2HET2[22] T7 PINMMR98[24] N1 PINMMR98[25]
29Ch nTZ1_1 N19 PINMMR99[0] C3 PINMMR99[1]
nTZ1_2 F1 PINMMR99[8] B2 PINMMR99[9]
nTZ1_3 J3 PINMMR99[16] D19 PINMMR99[17]