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Clock0

reload

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Counter1 does not reach 0

Clock1

Valid0

Error

before VALID0 reaches 0

Count1

time

Clock0

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Clock1

Valid0

in this window, otherwise

signal an error

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Count1

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Module Operation

545

SPNU563A–March 2018

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Dual-Clock Comparator (DCC) Module

Figure 15-2. Counter Relationship

Figure 15-3. Clock1 Slower Than Clock0 - Results in an Error and Stops Counting

Default Chapter2
- Table of Contents2
Preface104
1 Introduction106
- Designed for Safety Applications107
- Family Description108
- Endianism Considerations111
  - TMS570: Big Endian (BE32)111
2 Architecture112
- Introduction113
- Memory Organization120
- Exceptions139
- Clocks142
- System and Peripheral Control Registers151
3 SCR Control Module (SCM)252
- Overview253
  - Features253
  - System Block Diagram254
- Module Operation255
- How to Use SCM257
- SCM Registers260
4 Interconnect265
- Overview266
  - Block Diagram266
- Peripheral Interconnect Subsystem266
- CPU Interconnect Subsystem268
- SDC MMR Registers272
5 Power Management Module (PMM)279
- Overview280
  - Features280
  - Block Diagram280
- Power Domains282
- PMM Operation283
- PMM Registers285
- Logic Power Domain Control Register (LOGICPDPWRCTRL0)286
- Logic Power Domain Control Register (LOGICPDPWRCTRL1)287
- Power Domain Clock Disable Register (PDCLKDISREG)288
- Power Domain Clock Disable Set Register (PDCLKDISSETREG)289
6 I/O Multiplexing and Control Module (IOMM)301
- Overview302
- Main Features of I/O Multiplexing Module (IOMM)302
- Control of Multiplexed Outputs302
- Control of Multiplexed Inputs303
- Control of Special Multiplexed Options312
- Safety Features327
  - Locking Mechanism for Memory-Mapped Registers327
  - Error Conditions327
- IOMM Registers328
7 F021 Level 2 Flash Module Controller (L2FMC)338
- Overview339
- Default Flash Configuration340
- EEPROM Emulation Support340
- Secded341
- Memory Map345
  - Location of Flash ECC Bits345
  - OTP Memory346
- Power On, Power off Considerations350
  - Error Checking at Power on350
  - Flash Integrity at Power off350
- Emulation and SIL3 Diagnostic Modes350
- Parameter Overlay Module (POM)353
  - Example Procedure to Configure the POM353
- Summary of L2FMC Errors354
- Flash Control Registers355
- POM Control Registers383
8 Level 2 RAM (L2RAMW) Module387
- Overview388
- Module Operation388
- Control and Status Registers393
9 Programmable Built-In Self-Test (PBIST) Module405
- Overview406
- RAM Grouping and Algorithm407
- PBIST Flow408
  - PBIST Sequence409
- Memory Test Algorithms on the On-Chip ROM411
- PBIST Control Registers412
- PBIST Configuration Example426
  - Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM426
  - Example 2 : Configuration of PBIST Controller to Run Self-Test on ALL RAM Groups427
10 Self-Test Controller (STC) Module428
- General Description429
- STC Module Assignments436
- STC Programmers Flow437
- Application Self-Test Flow438
- STC1 Segment 0 (CPU) Test Coverage and Duration441
- STC1 Segment 1 (Μscu) Test Coverage and Duration444
- STC2 (Nhet) Test Coverage and Duration444
- STC Control Registers446
- STC Configuration Example458
  - Example: STC1 Self-Test Run458
- Self-Test Controller Diagnostics459
11 System Memory Protection Unit (NMPU)460
- Overview461
- Module Operation463
- How to Use NMPU466
  - How to Use NMPU in Functional Mode466
  - How to Use Diagnostics468
- NMPU Registers471
- MPU Revision ID Register (MPUREV)472
12 Error Profiling Controller (EPC)483
- Overview484
- Module Operation484
  - Uncorrectable Fault Operation485
  - Correctable Fault Operation485
- How to Use EPC487
  - Functional Mode487
  - CAM Diagnostic Mode488
- EPC Control Registers488
13 CPU Compare Module for Cortex-R5F (CCM-R5F)497
- Overview498
  - Main Features498
  - Block Diagram498
- Module Operation499
- Control Registers507
14 Oscillator and PLL517
- Introduction518
  - Features518
- Quick Start519
- Oscillator520
- Low Power Oscillator and Clock Detect (LPOCLKDET)522
- Pll525
- PLL Control Registers534
- Phase-Locked Loop Theory of Operation538
- Programming Example540
15 Dual-Clock Comparator (DCC) Module542
- Introduction543
  - Main Features543
  - Block Diagram543
- Module Operation544
  - Continuous Monitoring Mode544
  - Single-Shot Measurement Mode547
- Clock Source Selection for Counter0 and Counter1548
- DCC Control Registers549
17 Real-Time Interrupt (RTI) Module583
- Overview584
  - Features584
  - Industry Standard Compliance Statement584
- Module Operation585
  - Counter Operation585
  - Interrupt/Dma Requests587
  - RTI Clocking588
  - Synchronizing Timer Events to Network Time (NTU)588
  - Digital Watchdog (DWD)591
  - Low Power Modes594
  - Halting Debug Mode Behaviour594
- RTI Control Registers595
- RTI Global Control Register (RTIGCTRL)596
- Power down Mode637
- Emulation637
- Peripheral Bus Interface638
- Example638
- Example: Auto Mode Using Time Based Event Triggering638
- Example: Auto Mode Without Using Time Based Triggering639
- Example: Semi-CPU Mode640
- Example: Full-CPU Mode640
- CRC Control Registers641
- CRC Global Control Register 0 (CRC_CTRL0)642
- CRC Global Control Register (CRC_CTRL1)642
- CRC Global Control Register 2 (CRC_CTRL2)643
- CRC Interrupt Enable Set Register (CRC_INTS)644
- CRC Interrupt Enable Reset Register (CRC_INTR)646
- CRC Interrupt Status Register (CRC_STATUS)648
- CRC Interrupt Offset (CRC_INT_OFFSET_REG)650
- CRC Busy Register (CRC_BUSY)651
- CRC Pattern Counter Preload Register 1 (CRC_PCOUNT_REG1)651
- CRC Sector Counter Preload Register 1 (CRC_SCOUNT_REG1)652
- CRC Current Sector Register 1 (CRC_CURSEC_REG1)652
- CRC Channel 1 Watchdog Timeout Preload Register a (CRC_WDTOPLD1)653
- CRC Channel 1 Block Complete Timeout Preload Register B (CRC_BCTOPLD1)653
- Channel 1 PSA Signature Low Register (PSA_SIGREGL1)654
- Channel 1 PSA Signature High Register (PSA_SIGREGH1)654
- Channel 1 CRC Value Low Register (CRC_REGL1)654
- Channel 1 CRC Value High Register (CRC_REGH1)655
- Channel 1 PSA Sector Signature Low Register (PSA_SECSIGREGL1)655
- Channel 1 PSA Sector Signature High Register (PSA_SECSIGREGH1)655
- Channel 1 Raw Data Low Register (RAW_DATAREGL1)656
- Channel 1 Raw Data High Register (RAW_DATAREGH1)656
- CRC Pattern Counter Preload Register 2 (CRC_PCOUNT_REG2)656
- CRC Sector Counter Preload Register 2 (CRC_SCOUNT_REG2)657
- CRC Current Sector Register 2 (CRC_CURSEC_REG2)657
- CRC Channel 2 Watchdog Timeout Preload Register a (CRC_WDTOPLD2)658
- CRC Channel 2 Block Complete Timeout Preload Register B (CRC_BCTOPLD2)658
- Channel 2 PSA Signature Low Register (PSA_SIGREGL2)659
- Channel 2 PSA Signature High Register (PSA_SIGREGH2)659
- Channel 2 CRC Value Low Register (CRC_REGL2)659
- Channel 2 CRC Value High Register (CRC_REGH2)660
- Channel 2 PSA Sector Signature Low Register (PSA_SECSIGREGL2)660
- Channel 2 PSA Sector Signature High Register (PSA_SECSIGREGH2)660
- Channel 2 Raw Data Low Register (RAW_DATAREGL2)661
- Channel 2 Raw Data High Register (RAW_DATAREGH2)661
- Vectored Interrupt Manager (VIM) Module662
- Overview663
- Dual VIM for Safety664
- Device Level Interrupt Management665
- Interrupt Generation at the Peripheral665
- Interrupt Handling at the CPU666
- Software Interrupt Handling Options667
- Interrupt Handling Inside VIM668
- VIM Interrupt Channel Mapping669
- VIM Input Channel Management671
- Interrupt Vector Table (VIM RAM)672
- Interrupt Vector Table Operation672
- VIM ECC Syndrome673
- Interrupt Vector Table Initialization674
- Interrupt Vector Table ECC Testing674
- VIM Wakeup Interrupt676
- Capture Event Sources677
- Examples677
- Examples - Configure CPU to Receive Interrupts677
- Examples - Register Vector Interrupt and Index Interrupt Handling678
- VIM Control Registers680
- Interrupt Vector Table ECC Status Register (ECCSTAT)681
- Interrupt Vector Table ECC Control Register (ECCCTL)682
- Uncorrectable Error Address Register (UERRADDR)683
- Fallback Vector Address Register (FBVECADDR)683
- Single-Bit Error Address Register (SBERRADDR)684
- VIM Offset Vector Registers684
- IRQ Index Offset Vector Register (IRQINDEX)685
- FIQ Index Offset Vector Registers (FIQINDEX)685
- FIQ/IRQ Program Control Registers (FIRQPR[0:3])686
- Pending Interrupt Read Location Registers (INTREQ[0:3])687
- Interrupt Enable Set Registers (REQENASET[0:3])688
- Interrupt Enable Clear Registers (REQENACLR[0:3])689
- Wake-Up Enable Set Registers (WAKEENASET[0:3])690
- Wake-Up Enable Clear Registers (WAKEENACLR[0:3])691
- IRQ Interrupt Vector Register (IRQVECREG)692
- FIQ Interrupt Vector Register (FIQVECREG)692
- Capture Event Register (CAPEVT)693
- VIM Interrupt Control Registers (CHANCTRL[0:31])694
- Direct Memory Access Controller (DMA) Module696
- Overview697
- Main Features697
- System Resources Mapping699
- Module Operation699
- Memory Space700
- DMA Data Access700
- Addressing Modes701
- DMA Channel Control Packets701
- Priority Queue705
- Data Packing and Unpacking707
- DMA Request710
- Auto-Initiation712
- Interrupts712
- Debugging714
- Power Management714
- FIFO Buffer715
- Channel Chaining716
- Request Polarity716
- Memory Protection717
- ECC Checking718
- ECC Testing719
- Initializing RAM with ECC719
- Transaction Errors720
- Submit Documentation Feedback720
- Copyright © 2018, Texas Instruments Incorporated720
- Control Registers and Control Packets721
- Global Configuration Registers724
- Channel Configuration788
- External Memory Interface (EMIF)793
21 External Memory Interface (EMIF)794
- Introduction794
- Purpose of the Peripheral794
- Features794
- Functional Block Diagram795
- EMIF Module Architecture796
- EMIF Clock Control796
- EMIF Requests796
- EMIF Signal Descriptions796
- EMIF Signal Multiplexing Control797
- SDRAM Controller and Interface798
- Asynchronous Controller and Interface810
- Data Bus Parking822
- Reset and Initialization Considerations823
- Interrupt Support823
- DMA Event Support824
- EMIF Signal Multiplexing824
- Memory Map824
- Priority and Arbitration825
- System Considerations826
- Power Management827
- Emulation Considerations827
- EMIF Registers828
- Module ID Register (MIDR)828
- Asynchronous Wait Cycle Configuration Register (AWCC)829
- SDRAM Configuration Register (SDCR)830
- SDRAM Refresh Control Register (SDRCR)831
- Asynchronous N Configuration Registers (CE2CFG-CE5CFG)832
- SDRAM Timing Register (SDTIMR)833
- SDRAM Self Refresh Exit Timing Register (SDSRETR)834
- EMIF Interrupt Raw Register (INTRAW)835
- EMIF Interrupt Masked Register (INTMSK)836
- EMIF Interrupt Mask Set Register (INTMSKSET)837
- EMIF Interrupt Mask Clear Register (INTMSKCLR)838
- Page Mode Control Register (PMCR)839
- Example Configuration840
- Hardware Interface840
- Software Configuration840
- Analog to Digital Converter (ADC) Module848
22 Analog to Digital Converter (ADC) Module849
- Overview849
- Introduction851
- Basic Operation853
- Basic Features and Usage of the ADC853
- Advanced Conversion Group Configuration Options860
- ADC Module Basic Interrupts868
- ADC Module DMA Requests869
- ADC Magnitude Threshold Interrupts870
- ADC Special Modes871
- ADC Results' RAM Special Features878
- ADEVT Pin General Purpose I/O Functionality879
- ADC Group2 Sample Cap Discharge Control Register (ADG2SAMPDISEN)937
- ADC Magnitude Compare Interrupt Control Registers (Admagintxcr)938
- ADC Magnitude Compare Interruptx Mask Register (Admagintxmask)940
- ADC Magnitude Compare Interrupt Enable Set Register (ADMAGINTENASET)941
- ADC Magnitude Compare Interrupt Enable Clear Register (ADMAGINTENACLR)941
- ADC Magnitude Compare Interrupt Flag Register (ADMAGINTFLG)942
- ADC Magnitude Compare Interrupt Offset Register (ADMAGINTOFF)942
- ADC Event Group FIFO Reset Control Register (ADEVFIFORESETCR)943
- ADC Group1 FIFO Reset Control Register (ADG1FIFORESETCR)943
- ADC Group2 FIFO Reset Control Register (ADG2FIFORESETCR)944
- ADC Event Group RAM Write Address Register (ADEVRAMWRADDR)944
- ADC Group1 RAM Write Address Register (ADG1RAMWRADDR)945
- ADC Group2 RAM Write Address Register (ADG2RAMWRADDR)945
- ADC Parity Control Register (ADPARCR)946
- ADC Parity Error Address Register (ADPARADDR)947
- ADC Power-Up Delay Control Register (ADPWRUPDLYCTRL)947
- ADC Event Group Channel Selection Mode Control Register (ADEVCHNSELMODECTRL)948
- ADC Group1 Channel Selection Mode Control Register (ADG1CHNSELMODECTRL)948
- ADC Group2 Channel Selection Mode Control Register (ADG2CHNSELMODECTRL)949
- ADC Event Group Current Count Register (ADEVCURRCOUNT)950
- ADC Event Group Maximum Count Register (ADEVMAXCOUNT)950
- ADC Group1 Current Count Register (ADG1CURRCOUNT)951
- ADC Group1 Maximum Count Register (ADG1MAXCOUNT)951
- ADC Group2 Current Count Register (ADG2CURRCOUNT)952
- ADC Group2 Maximum Count Register (ADG2MAXCOUNT)952
- High-End Timer (N2HET) Module953
23 High-End Timer (N2HET) Module954
- Overview954
- Features954
- Major Advantages954
- Block Diagram955
- Timer Module Structure and Execution956
- Performance957
- N2HET Compared to NHET957
- NHET and N2HET Compared to HET957
- Instructions Features958
- Program Usage958
- N2HET Functional Description958
- Specialized Timer Micromachine958
- N2HET RAM Organization963
- Time Base966
- Host Interface969
- I/O Control970
- Suppression Filters986
- Interrupts and Exceptions987
- Hardware Priority Scheme988
- N2HET Requests to DMA and HTU990
- Angle Functions990
- Software Angle Generator990
- Hardware Angle Generator (HWAG)995
- Hardware Angle Generator/High End Timer Interface995
- N2HET Control Registers1017
- Global Configuration Register (HETGCR) [Offset = 00H]1017
- Global Configuration Register (HETGCR)1018
- Prescale Factor Register (HETPFR)1020
- N2HET Current Address Register (HETADDR)1021
- Offset Index Priority Level 1 Register (HETOFF1)1021
- N2HET Current Address (HETADDR)1021
- Offset Index Priority Level 2 Register (HETOFF2)1022
- Interrupt Enable Set Register (HETINTENAS)1023
- Interrupt Enable Clear Register (HETINTENAC)1023
- Exception Control Register 1 (HETEXC1)1024
- Exception Control Register 2 (HETEXC2)1025
- Interrupt Priority Register (HETPRY)1026
- Interrupt Flag Register (HETFLG)1026
- AND Share Control Register (HETAND)1027
- HR Share Control Register (HETHRSH)1028
- XOR Share Control Register (HETXOR)1029
- Request Enable Set Register (HETREQENS)1030
- Request Enable Clear Register (HETREQENC)1030
- Request Destination Select Register (HETREQDS)1031
- NHET Direction Register (HETDIR)1032
- N2HET Data Input Register (HETDIN)1033
- N2HET Data Output Register (HETDOUT)1033
- NHET Data Set Register (HETDSET)1034
- N2HET Data Clear Register (HETDCLR)1034
- N2HET Open Drain Register (HETPDR)1035
- N2HET Pull Disable Register (HETPULDIS)1035
- N2HET Pull Select Register (HETPSL)1036
- Parity Control Register (HETPCR)1037
- Parity Address Register (HETPAR)1038
- Parity Pin Register (HETPPR)1039
- Suppression Filter Preload Register (HETSFPRLD)1040
- Suppression Filter Enable Register (HETSFENA)1040
- Loop Back Pair Select Register (HETLBPSEL)1041
- Loop Back Pair Direction Register (HETLBPDIR)1042
- N2HET Pin Disable Register (HETPINDIS)1043
- HWAG Registers1044
- HWAG Pin Select Register (HWAPINSEL)1045
- HWAG Global Control Register 0 (HWAGCR0)1046
- HWAG Global Control Register 1 (HWAGCR1)1046
- HWAG Global Control Register 2 (HWAGCR2)1047
- HWAG Interrupt Enable Set Register (HWAENASET)1048
- HWAG Interrupt Enable Clear Register (HWAENACLR)1049
- HWAG Interrupt Level Set Register (HWALVLSET)1050
- HWAG Interrupt Level Clear Register (HWALVLCLR)1050
- HWAG Interrupt Flag Register (HWAFLG)1051
- HWAG Interrupt Offset Register 0 (HWAOFF0)1052
- HWAG Interrupt Offset Register 1 (HWAOFF1)1053
- HWAG Angle Value Register (HWAACNT)1054
- HWAG Previous Tooth Period Value Register (HWAPCNT1)1055
- HWAG Current Tooth Period Value Register (HWAPCNT)1055
- HWAG Step Width Register (HWASTWD)1056
- HWAG Teeth Number Register (HWATHNB)1057
- HWAG Current Teeth Number Register (HWATHVL)1057
- HWAG Filter Register (HWAFIL)1058
- HWAG Filter Register 2 (HWAFIL2)1058
- HWAG Angle Increment Register (HWAANGI)1059
- Instruction Set1060
- Instruction Summary1060
- Abbreviations, Encoding Formats and Bits1062
- Instruction Description1065
- High-End Timer Transfer Unit (HTU) Module1131
24 High-End Timer Transfer Unit (HTU) Module1132
- Overview1132
- Features1132
- Module Operation1133
- Data Transfers between Main RAM and N2HET RAM1135
- Arbitration of HTU Elements and Frames1139
- Conditions for Frame Transfer Interruption1140
- HTU Overload and Request Lost Detection1140
- Memory Protection1143
- Control Packet RAM Parity Checking1143
- Use Cases1145
- Example: Single Element Transfer with One Trigger Request1145
- Example: Multiple Element Transfer with One Trigger Request1145
- Example: 64-Bit-Transfer of Control Field and Data Fields1147
- HTU Control Registers1148
- Global Control Register (HTU GC)1149
- Control Packet Enable Register (HTU CPENA)1150
- Control Packet (CP) Busy Register 0 (HTU BUSY0)1151
- Control Packet (CP) Busy Register 1 (HTU BUSY1)1152
- Control Packet (CP) Busy Register 2 (HTU BUSY2)1152
- Control Packet (CP) Busy Register 3 (HTU BUSY3)1153
- Active Control Packet and Error Register (HTU ACPE)1153
- Request Lost and Bus Error Control Register (HTU RLBECTRL)1155
- Buffer Full Interrupt Enable Set Register (HTU BFINTS)1156
- Buffer Full Interrupt Enable Clear Register (HTU BFINTC)1156
- Interrupt Mapping Register (HTU INTMAP)1157
- Interrupt Offset Register 0 (HTU INTOFF0)1158
- Interrupt Offset Register 1 (HTU INTOFF1)1159
- Buffer Initialization Mode Register (HTU BIM)1160
- Request Lost Flag Register (HTU RLOSTFL)1162
- Buffer Full Interrupt Flag Register (HTU BFINTFL)1162
- BER Interrupt Flag Register (HTU BERINTFL)1163
- Memory Protection 1 Start Address Register (HTU MP1S)1164
- Memory Protection 1 End Address Register (HTU MP1E)1164
- Debug Control Register (HTU DCTRL)1165
- Watch Point Register (HTU WPR)1166
- Watch Mask Register (HTU WMR)1166
- Module Identification Register (HTU ID)1167
- Parity Control Register (HTU PCR)1168
- Parity Address Register (HTU PAR)1169
- Memory Protection Control and Status Register (HTU MPCS)1170
- Memory Protection Start Address Register 0 (HTU MP0S)1173
- Memory Protection End Address Register (HTU MP0E)1173
- Double Control Packet Configuration Memory1174
- Initial Full Address a Register (HTU IFADDRA)1175
- Initial Full Address B Register (HTU IFADDRB)1175
- Initial N2HET Address and Control Register (HTU IHADDRCT)1176
- Initial Transfer Count Register (HTU ITCOUNT)1177
- Current Full Address a Register (HTU CFADDRA)1178
- Current Full Address B Register (HTU CFADDRB)1179
- Current Frame Count Register (HTU CFCOUNT)1180
- Examples1181
- Application Examples for Setting the Transfer Modes of CP a and B of a DCP1181
- Software Example Sequence Assuming Circular Mode for both CP a and B1181
- Example of an Interrupt Dispatch Flow for a Request Lost Interrupt1182
- General-Purpose Input/Output (GIO) Module1183
25 General-Purpose Input/Output (GIO) Module1184
- Overview1184
- Quick Start Guide1185
- Functional Description of GIO Module1187
- I/O Functions1187
- Interrupt Function1188
- GIO Block Diagram1188
- Device Modes of Operation1190
- Emulation Mode1190
- Power-Down Mode (Low-Power Mode)1190
- GIO Control Registers1191
- GIO Global Control Register (GIOGCR0)1192
- GIO Interrupt Detect Register (GIOINTDET)1193
- GIO Interrupt Polarity Register (GIOPOL)1194
- GIO Interrupt Enable Registers (GIOENASET and GIOENACLR)1195
- GIO Interrupt Priority Registers (GIOLVLSET and GIOLVLCLR)1197
- GIO Interrupt Flag Register (GIOFLG)1200
- GIO Offset Register 1 (GIOOFF1)1201
- GIO Offset B Register (GIOOFF2)1202
- GIO Emulation a Register (GIOEMU1)1203
- GIO Emulation B Register (GIOEMU2)1204
- GIO Data Direction Registers (GIODIR[A-B])1205
- GIO Data Input Registers (GIODIN[A-B])1205
- GIO Data Output Registers (GIODOUT[A-B])1206
- GIO Data Set Registers (GIODSET[A-B])1206
- GIO Data Clear Registers (GIODCLR[A-B])1207
- GIO Open Drain Registers (GIOPDR[A-B])1207
- GIO Pull Disable Registers (GIOPULDIS[A-B])1208
- GIO Pull Select Registers (GIOPSL[A-B])1208
- I/O Control Summary1209
- Flexray Module1210
26 Flexray Module1211
- Overview1211
- Feature List1211
- Flexray Module Block Diagram1211
- Flexray Module Blocks1214
- Module Operation1215
- Transfer Unit1215
- Communication Cycle1226
- Communication Modes1227
- Clock Synchronization1228
- Error Handling1229
- Communication Controller States1231
- Network Management1243
- Filtering and Masking1243
- Transmit Process1246
- Receive Process1248
- FIFO Function1249
- Message Handling1250
- Module Rams1258
- Interrupts1269
- Minimum Peripheral Clock Frequency1274
- Assignment of Flexray Configuration Parameters1275
- Emulation/Debug Support1276
- Flexray Module Registers1277
- Transfer Unit Registers1277
- Communication Controller Registers1325
- Controller Area Network (DCAN) Module1417
27 Controller Area Network (DCAN) Module1418
- Overview1418
- Features1418
- Functional Description1418
- CAN Blocks1419
- CAN Core1419
- Message RAM1419
- Message Handler1419
- Message RAM Interface1420
- Register and Message Object Access1420
- Dual Clock Source1420
- CAN Bit Timing1421
- Bit Time and Bit Rate1421
- DCAN Bit Timing Registers1423
- CAN Module Configuration1425
- DCAN RAM Initialization through Hardware1425
- CAN Module Initialization1425
- Message RAM1428
- Structure of Message Objects1428
- Addressing Message Objects in RAM1430
- Message RAM Representation in Debug/Suspend Mode1431
- Message RAM Representation in Direct Access Mode1431
- Ecc Ram1432
- Message Interface Register Sets1433
- Message Interface Register Sets 1 and 21433
- Using Message Interface Register Sets 1 and 21434
- Message Interface Register 31435
- Message Object Configurations1436
- Configuration of a Transmit Object for Data Frames1436
- Configuration of a Transmit Object for Remote Frames1436
- Configuration of a Single Receive Object for Data Frames1436
- Configuration of a Single Receive Object for Remote Frames1437
- Configuration of a FIFO Buffer1437
- Reconfiguration of Message Objects for the Reception of Frames1437
- Reconfiguration of Message Objects for the Transmission of Frames1437
- Message Handling1438
- Message Handler Overview1438
- Receive/Transmit Priority1438
- Transmission of Messages in Event Driven CAN Communication1439
- Updating a Transmit Object1439
- Changing a Transmit Object1439
- Acceptance Filtering of Received Messages1440
- Reception of Data Frames1440
- Reception of Remote Frames1440
- Reading Received Messages1440
- Requesting New Data for a Receive Object1441
- Parity Error Code Register (DCAN PERR) [Offset = 1Ch]1465
- Core Release Register (DCAN REL) [Offset = 20H]1465
- ECC Diagnostic Register (DCAN ECCDIAG) [Offset = 24H]1466
- ECC Diagnostic Status Register (DCAN ECCDIAG STAT) [Offset = 28H]1466
- Auto-Bus-On Time Register (DCAN ABOTR) [Offset = 80H]1469
- Transmission Request X Register (DCAN TXRQ X) [Offset = 84H]1469
- Transmission Request 12 Register (DCAN TXRQ12) [Offset = 88H]1470
- Transmission Request 34 Register (DCAN TXRQ34) [Offset = 8Ch]1470
- Transmission Request 56 Register (DCAN TXRQ56) [Offset = 90H]1470
- Transmission Request 78 Register (DCAN TXRQ78) [Offset = 94H]1470
- New Data X Register (DCAN NWDAT X) [Offset = 98H]1471
- New Data 12 Register (DCAN NWDAT12) [Offset = 9Ch]1472
- New Data 34 Register (DCAN NWDAT34) [Offset = A0H]1472
- New Data 56 Register (DCAN NWDAT56) [Offset = A4H]1472
- New Data 78 Register (DCAN NWDAT78) [Offset = A8H]1472
- Interrupt Pending X Register (DCAN INTPND X) [Offset = Ach]1473
- Interrupt Pending 12 Register (DCAN INTPND12) [Offset = B0H]1474
- Interrupt Pending 34 Register (DCAN INTPND34) [Offset = B4H]1474
- Interrupt Pending 56 Register (DCAN INTPND56) [Offset = B8H]1474
- Interrupt Pending 78 Register (DCAN INTPND78) [Offset = Bch]1474
- Message Valid X Register (DCAN MSGVAL X) [Offset = C0H]1475
- Message Valid 12 Register (DCAN MSGVAL12) [Offset = C4H]1476
- Message Valid 34 Register (DCAN MSGVAL34) [Offset = C8H]1476
- Message Valid 56 Register (DCAN MSGVAL56) [Offset = Cch]1476
- Message Valid 78 Register (DCAN MSGVAL78) [Offset = D0H]1476
- Interrupt Multiplexer 12 Register (DCAN INTMUX12) [Offset = D8H]1477
- Interrupt Multiplexer 34 Register (DCAN INTMUX34) [Offset = Dch]1477
- Interrupt Multiplexer 56 Register (DCAN INTMUX56) [Offset = E0H]1477
- Interrupt Multiplexer 78 Register (DCAN INTMUX78) [Offset = E4H]1477
- IF1 Command Registers (DCAN IF1CMD) [Offset = 100H]1478
- IF1 Mask Register (DCAN IF1MSK) [Offset = 104H]1481
- IF1 Arbitration Register (DCAN IF1ARB) [Offset = 108H]1482
- IF1 Message Control Register (DCAN IF1MCTL) [Offset = 10Ch]1484
- IF1 Data a Register (DCAN IF1DATA) [Offset = 110H]1486
- IF1 Data B Register (DCAN IF1DATB) [Offset = 114H]1486
- IF3 Observation Register (DCAN IF3OBS) [Offset = 140H]1487
- IF3 Mask Register (DCAN IF3MSK) [Offset = 144H]1489
- IF3 Arbitration Register (DCAN IF3ARB) [Offset = 148H]1490
- IF3 Message Control Register (DCAN IF3MCTL) [Offset = 14Ch]1491
- IF3 Data a Register (DCAN IF3DATA) [Offset = 150H]1492
- IF3 Data B Register (DCAN IF3DATB) [Offset = 154H]1492
- IF3 Update Enable 12 Register (DCAN IF3UPD12) [Offset = 160H]1493
- IF3 Update Enable 34 Register (DCAN IF3UPD34) [Offset = 164H]1493
- IF3 Update Enable 56 Register (DCAN IF3UPD56) [Offset = 168H]1493
- IF3 Update Enable 78 Register (DCAN IF3UPD78) [Offset = 16Ch]1493
- CAN TX IO Control Register (DCAN TIOC) [Offset = 1E0H]1494
- CAN RX IO Control Register (DCAN RIOC) [Offset = 1E4H]1495
- SPI Functional Logic Diagram1501
- Mibspi Functional Logic Diagram1502
- SPI Three-Pin Operation1507
- SPI Five-Pin Option with SPIENA and SPICS1510
- C2TDELAY = 8 VCLK Cycles1515
- T2CDELAY = 4 VCLK Cycles1516
- SPI Global Control Register 0 (SPIGCR0) [Offset = 00H]1536
- SPI Global Control Register 1 (SPIGCR1) [Offset = 04H]1537
- SPI Interrupt Register (SPIINT0) [Offset = 08H]1538
- SPI Interrupt Level Register (SPILVL) [Offset = 0Ch]1540
- SPI Flag Register (SPIFLG) [Offset = 10H]1541
- SPI Pin Control Register 0 (SPIPC0) [Offset = 14H]1544
- SPI Pin Control Register 1 (SPIPC1) [Offset = 18H]1545
- SPI Pin Control Register 2 (SPIPC2) [Offset = 1Ch]1547
- SPI Pin Control Register 3 (SPIPC3) [Offset = 20H]1548
- SPI Pin Control Register 4 (SPIPC4) [Offset = 24H]1549
- SPI Pin Control Register 5 (SPIPC5) [Offset = 28H]1551
- SPI Pin Control Register 6 (SPIPC6) [Offset = 2Ch]1552
- SPI Pin Control Register 7 (SPIPC7) [Offset = 30H]1554
- SPI Pin Control Register 8 (SPIPC8) [Offset = 34H]1555
- SPI Transmit Data Register 0 (SPIDAT0) [Offset = 38H]1556
- SPI Transmit Data Register 1 (SPIDAT1) [Offset = 3Ch]1557
- SPI Receive Buffer Register (SPIBUF) [Offset = 40H]1560
- SPI Emulation Register (SPIEMU) [Offset = 44H]1562
- SPI Delay Register (SPIDELAY) [Offset = 48H]1562
- VCLK Cycles1564
- SPNU563A - March2018

Brand	Texas Instruments
Model	TMS570LC4357
Category	Microcontrollers
Language	English

Texas Instruments TMS570LC4357 User Manual

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Texas Instruments TMS570LC4357 Specifications

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