Module Operation
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SPNU563A–March 2018
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Cyclic Redundancy Check (CRC) Controller Module
The current sector register is frozen from being updated until both the current sector register is read and
CRC fail status bit is cleared by CPU. If CPU does not respond to the CRC failure in a timely manner
before another sector produces a signature verification failure, the current sector register is not updated
with the new sector number. An overrun interrupt is generate instead. If current sector register is already
frozen with an erroneous sector and emulation is entered with SUSPEND signal goes to high then the
register still remains frozen even it is read.
In Semi-CPU mode, the current sector register is used to indicate the sector for which the compression
complete has last happened.
The current sector register is reset when the PSA software reset is enabled.
NOTE: Both data pattern count and sector count registers must be greater than or equal to one for
the counters to count. After reset, pattern count and sector count registers default to zero
and the associated counters are inactive.
18.2.10 Interrupt
The CRC controller generates several types of interrupts per channel. Associated with each interrupt,
there is an interrupt enable bit. No interrupt is generated in Full-CPU mode.
• Compression complete interrupt
• CRC fail interrupt
• Overrun interrupt
• Underrun interrupt
• Timeout interrupt
Table 18-2. Modes in Which Interrupt Condition Can Occur
AUTO Semi-CPU Full-CPU
Compression Complete no yes no
CRC Fail yes no no
Overrun yes yes no
Underrun yes no no
Timeout yes yes no
18.2.10.1 Compression Complete Interrupt
Compression complete interrupt is generated in Semi-CPU mode only. When the data pattern counter
reaches zero, the compression complete flag is set and the interrupt is generated.
18.2.10.2 CRC Fail Interrupt
CRC fail interrupt is generated in AUTO mode only. When the signature verification fails, the CRC fail flag
is set,. CPU should take action to address the fail condition and clear the CRC fail flag after it resolves the
CRC mismatch.
18.2.10.3 Overrun Interrupt
Overrun interrupt is generated in either AUTO or Semi-CPU mode. During AUTO mode, if a CRC fail is
detected then the current sector number is recorded in the current sector register. If CRC fail status bit is
not cleared and current sector register is not read by the host CPU before another CRC fail is detected for
another sector then an overrun interrupt is generated. During Semi-CPU mode, when the data pattern
counter finishes counting, it generates a compression complete interrupt. At the same time the signature is
copied into the PSA Sector Signature Register. If the host CPU does not read the signature from PSA
Sector Signature Register before it is updated again with a new signature value then an overrun interrupt
is generated.
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