Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.45 HBCA Interrupt Channel Offset Register (HBCAOFFSET)
Figure 20-62. HBCA Interrupt Channel Offset Register (HBCAOFFSET) [offset = 154h]
31 16
Reserved
R-0
15 8 7 6 5 0
Reserved sbz sbz HBCA
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 20-52. HBCA Interrupt Channel Offset Register (HBCAOFFSET) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reads return 0. Writes have no effect.
7-6 sbz 0 These bits should always be programmed as zero.
5-0 HBCA Channel causing HBC interrupt Group A. These bits contain the channel number of the pending
interrupt for Group A if the corresponding interrupt enable is set.
Note: Reading this location clears the corresponding interrupt pending flag (see
Section 20.3.1.40) with the highest priority.
0 No interrupt is pending.
1h Channel 0 is causing the pending interrupt Group A.
: :
20h Channel 31 is causing the pending interrupt Group A.
21h-
3Fh
Reserved
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