Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.39 LFS Interrupt Flag Register (LFSFLAG)
Figure 20-57. LFS Interrupt Flag Register (LFSFLAG) [offset = 12Ch]
31 0
LFSI[31:0]
R/W1CP-0
LEGEND: R/W = Read/Write;W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 20-47. LFS Interrupt Flag Register (LFSFLAG) Field Descriptions
Bit Field Value Description
31-0 LFSI[n] Last frame started (LFS) flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so
on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 20.3.1.44 and Section 20.3.1.48 ).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0 Read: LFS interrupt of the corresponding channel is not pending.
Write: No effect.
1 Read: LFS interrupt of the corresponding channel is pending.
Write: The flag is cleared.
20.3.1.40 HBC Interrupt Flag Register (HBCFLAG)
Figure 20-58. HBC Interrupt Flag Register (HBCFLAG) [offset = 134h]
31 0
HBCI[31:0]
R/W1CP-0
LEGEND: R/W = Read/Write; W1CP = Write 1 to clear in privilege mode only; -n = value after reset
Table 20-48. HBC Interrupt Flag Register (HBCFLAG) Field Descriptions
Bit Field Value Description
31-0 HBCI[n] Half block transfer (HBC) complete flags. Bit 0 corresponds to channel 0, bit 1 corresponds to channel
1, and so on.
Note: Reading from the respective interrupt channel offset register also clears the
corresponding flag (see Section 20.3.1.45and Section 20.3.1.49).
Note: The state of the flag bit can be polled even if the corresponding interrupt enable bit is
cleared.
0 Read: HBC interrupt of the corresponding channel is not pending.
Write: No effect.
1 Read: HBC interrupt of the corresponding channel is pending.
Write: The flag is cleared.
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