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Control Registers and Control Packets
765
SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.59 FIFO B Active Channel Source Address Register (FBACSADDR)
Figure 20-76. FIFO B Active Channel Source Address Register (FBACSADDR) [offset = 198h]
31 0
FBACSA
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-66. FIFO B Active Channel Source Address Register (FBACSADDR) Field Descriptions
Bit Field Description
31-0 FBACSA FIFO B Active Channel Source Address. This register contains the current source address of the active
channel as broadcasted in Section 20.3.1.3 for FIFO B.
20.3.1.60 FIFO B Active Channel Destination Address Register (FBACDADDR)
Figure 20-77. FIFO B Active Channel Destination Address Register (FBACDADDR) [offset = 19Ch]
31 0
FBACDA
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-67. FIFO B Active Channel Destination Address Register (FBACDADDR)
Field Descriptions
Bit Field Description
31-0 FBACDA FIFO B Active Channel Destination Address. This register contains the current destination address of the active
channel as broadcasted in Section 20.3.1.3 for FIFO B.
20.3.1.61 FIFO B Active Channel Transfer Count Register (FBACTC)
Figure 20-78. FIFO B Active Channel Transfer Count Register (FBACTC) [offset = 1A0h]
31 29 28 16
Reserved FBFTCOUNT
R-0 R-0
15 13 12 0
Reserved FBETCOUNT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 20-68. FIFO B Active Channel Transfer Count Register (FBACTC) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reads return 0. Writes have no effect.
28-16 FBFTCOUNT 0-1FFFh FIFO B active channel frame count. These bits contain the current frame count value of the
active channel as broadcasted in Section 20.3.1.3 for FIFO B.
15-13 Reserved 0 Reads return 0. Writes have no effect.
12-0 FBETCOUNT 0-1FFFh FIFO B active channel element count. These bits contain the current element count value of
the active channel as broadcasted in Section 20.3.1.3 for FIFO B.