Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.56 FIFO A Active Channel Source Address Register (FAACSADDR)
Figure 20-73. FIFO A Active Channel Source Address Register (FAACSADDR) [offset = 18Ch]
31 0
FAACSA
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-63. FIFO A Active Channel Source Address Register (FAACSADDR) Field Descriptions
Bit Field Description
31-0 FAACSA FIFO B Active Channel Source Address. This register contains the current source address of the active
channel as broadcasted in Section 20.3.1.3 for FIFO B.
20.3.1.57 FIFO A Active Channel Destination Address Register (FAACDADDR)
Figure 20-74. FIFO A Active Channel Destination Address Register (FAACDADDR) [offset = 190h]
31 0
FAACDA
R-0
LEGEND: R = Read only; -n = value after reset
Table 20-64. FIFO A Active Channel Destination Address Register (FAACDADDR)
Field Descriptions
Bit Field Description
31-0 FAACDA FIFO A Active Channel Destination Address. This register contains the current destination address of the active
channel as broadcasted in Section 20.3.1.3 for FIFO A.
20.3.1.58 FIFO A Active Channel Transfer Count Register (FAACTC)
Figure 20-75. FIFO A Active Channel Transfer Count Register (FAACTC) [offset = 194h]
31 29 28 16
Reserved FAFTCOUNT
R-0 R-0
15 13 12 0
Reserved FAETCOUNT
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 20-65. Port B Active Channel Transfer Count Register (FAACTC) Field Descriptions
Bit Field Value Description
31-29 Reserved 0 Reads return 0. Writes have no effect.
28-16 FAFTCOUNT 0-1FFFh FIFO A active channel frame count. These bits contain the current frame count value of the
active channel as broadcasted in Section 20.3.1.3 for FIFO A.
15-13 Reserved 0 Reads return 0. Writes have no effect.
12-0 FAETCOUNT 0-1FFFh FIFO A active channel element count. These bits contain the current element count value of
the active channel as broadcasted in Section 20.3.1.3 for FIFO A.