Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
Table 20-81. DMA Memory Protection Control Register 2 (DMAMPCTRL2) Field Descriptions (continued)
Bit Field Value Description
15-13 Reserved 0 Reads return 0. Writes have no effect.
12 INT5AB Interrupt assignment of region 5 to Group A or Group B.
0 The interrupt is routed to the VIM (Group A).
1 The interrupt is routed to the second CPU (Group B).
11 INT5ENA Interrupt enable of region 5.
0 The interrupt is disabled.
1 The interrupt is enabled.
10-9 REG5AP Region 5 access permission. These bits determine the access permission for region 5.
0 All accesses are allowed.
1h Read only accesses are allowed.
2h Write only accesses are allowed.
3h No accesses are allowed.
8 REG5ENA Region 5 enable.
0 The region is disabled (no address checking done).
1 The region is enabled (address and access permission checking done).
7-5 Reserved 0 Reads return zeros and writes have no effect.
4 INT4AB Interrupt assignment of region 4 to Group A or Group B.
0 The interrupt is routed to the VIM (Group A).
1 The interrupt is routed to the second CPU (Group B).
3 INT4ENA Interrupt enable of region 4.
0 The interrupt is disabled.
1 The interrupt is enabled.
2-1 REG4AP Region 4 access permission. These bits determine the access permission for region 4.
0 All accesses are allowed.
1h Read only accesses are allowed.
2h Write only accesses are allowed.
3h No accesses are allowed.
0 REG4ENA Region 4 enable.
0 The region is disabled (no address checking done).
1 The region is enabled (address and access permission checking done).
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