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Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.75 DMA Memory Protection Status Register 2 (DMAMPST2)
Figure 20-92. DMA Memory Protection Status Register 2 (DMAMPST2) [offset = 1DCh]
31 25 24 23 17 16
Reserved REG7FT Reserved REG6FT
R-0 R/W1C-0 R-0 R/W1C-0
15 9 8 7 1 0
Reserved REG5FT Reserved REG4FT
R-0 R/W1C-0 R-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear; -n = value after reset
Table 20-82. DMA Memory Protection Status Register 2 (DMAMPST2) Field Descriptions
Bit Field Value Description
31-25 Reserved 0 Reads return 0. Writes have no effect.
24 REG7FT Region 7 fault. This bit determines whether an access permission violation was detected in this region.
0 Read: No fault was detected.
Write: No effect.
1 Read: A fault was detected.
Write: Clears the bit.
23-17 Reserved 0 Reads return 0. Writes have no effect.
16 REG6FT Region 6 fault. This bit determines whether a access permission violation was detected in this region.
0 Read: No fault was detected.
Write: No effect.
1 Read: A fault was detected.
Write: Clears the bit.
15-9 Reserved 0 Reads return 0. Writes have no effect.
8 REG5FT Region 5 fault. This bit determines whether an access permission violation was detected in this region.
0 Read: No fault was detected.
Write: No effect.
1 Read: A fault was detected.
Write: Clears the bit.
7-1 Reserved 0 Reads return 0. Writes have no effect.
0 REG4FT Region 4 fault. This bit determines whether a access permission violation was detected in this region.
0 Read: No fault was detected.
Write: No effect.
1 Read: A fault was detected.
Write: Clears the bit.
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