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EMIF Module Architecture
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SPNU563A–March 2018
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External Memory Interface (EMIF)
Table 21-15. Description of the Asynchronous m Configuration Register (CEnCFG) (continued)
Parameter Description
ASIZE Asynchronous Device Bus Width.
This field determines the data bus width of the asynchronous interface in the following way:
• ASIZE = 0 selects an 8-bit bus
• ASIZE = 1 selects a 16-bit bus
The configuration of ASIZE determines the function of the EMIF_A and EMIF_BA pins as
described in Section 21.2.6.1. This field also determines the number of external accesses
required to fulfill a request generated by one of the sources mentioned in Section 21.2.2. For
example, a request for a 32-bit word would require four external access when ASIZE = 0. Refer to
the datasheet of the external asynchronous device to determine the appropriate setting for this
field.
Table 21-16. Description of the Asynchronous Wait Cycle Configuration Register (AWCC)
Parameter Description
WPn EM_WAIT Polarity.
• WPn = 0 selects active-low polarity
• WPn = 1 selects active-high polarity
When set to 1, the EMIF will wait if the EMIF_nWAIT pin is high. When cleared to 0, the EMIF will
wait if the EMIF_nWAIT pin is low. The EMIF must have the Extended Wait Mode enabled for the
EMIF_nWAIT pin to affect the width of the strobe period.
MAX_EXT_WAIT Maximum Extended Wait Cycles.
This field configures the number of EMIF clock cycles the EMIF will wait for the EMIF_nWAIT pin
to be deactivated during the strobe period of an access cycle. The maximum number of EMIF
clock cycles it will wait is determined by the following formula:
Maximum Extended Wait Cycles = (MAX_EXT_WAIT + 1) × 16
If the EMIF_nWAIT pin is not deactivated within the time specified by this field, the EMIF resumes
the access cycle, registering whatever data is on the bus and proceeding to the hold period of the
access cycle. This situation is referred to as an Asynchronous Timeout. An Asynchronous
Timeout generates an interrupt, if it has been enabled in the EMIF interrupt mask set register
(INTMSKSET). Refer to Section 21.2.9.1 for more information about the EMIF interrupts.
Table 21-17. Description of the EMIF Interrupt Mask Set Register (INTMSKSET)
Parameter Description
WR_MASK_SET Wait Rise Mask Set.
Writing a 1 enables an interrupt to be generated when a rising edge on EMIF_nWAIT occurs
AT_MASK_SET Asynchronous Timeout Mask Set.
Writing a 1 to this bit enables an interrupt to be generated when an Asynchronous Timeout
occurs.
Table 21-18. Description of the EMIF Interrupt Mast Clear Register (INTMSKCLR)
Parameter Description
WR_MASK_CLR Wait Rise Mask Clear.
Writing a 1 to this bit disables the interrupt, clearing the WR_MASK_SET bit in the EMIF interrupt
mask set register (INTMSKSET).
AT_MASK_CLR Asynchronous Timeout Mask Clear.
Writing a 1 to this bit prevents an interrupt from being generated when an Asynchronous Timeout
occurs.
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