Texas Instruments TMS570LC4357 - Page 847

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847
SPNU563A–March 2018
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External Memory Interface (EMIF)
The W_SETUP and W_HOLD fields should combine to satisfy the Flash's nCE Pulse Width High
constraint, t
EHEL
, when performing back-to-back writes:
W_SETUP + W_HOLD > = t
EHEL
× f
EMIF_CLK
- 2
W_SETUP + W_HOLD > = 30 ns × 100 MHz - 2
W_SETUP + W_HOLD > = 1
In addition, the entire Write access length must satisfy the Flash's minimum Write Cycle Time, t
AVAV
:
W_SETUP + W_STROBE + W_HOLD >= t
AVAV
× f
EMIF_CLK
- 3
W_SETUP + W_STROBE + W_HOLD >= 90 ns × 100 MHz - 3
W_SETUP + W_STROBE + W_HOLD >= 6
Solving the above equations for the Write fields results in the following possible solution:
W_SETUP = 1
W_STROBE = 5
W_HOLD = 0
Adding a 10 ns (1 cycle) margin to each of the periods (excluding TA which is already at its maximum) in
this example produces the following recommended values:
W_SETUP = 2h
W_STROBE = 6h
W_HOLD = 1h
R_SETUP = 1h
R_STROBE = Bh
R_HOLD = 3h
TA = 3h
Figure 21-34. Asynchronous m Configuration Register (m = 1, 2) (CEnCFG (n = 2, 3))
31 30 29 26 25 24
1 0 0010 00
SS EW W_SETUP W_STROBE
23 20 19 17 16
0110 001 0
W_STROBE W_HOLD R_SETUP
15 13 12 7 6 4 3 2 1 0
001 001011 011 11 01
R_SETUP R_STROBE R_HOLD TA ASIZE