TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-44 V2.0, 2007-07
DMA, V2.0
Note: Register bits marked with “w” are virtual registers and do not contain flip-flops.
They are always read as 0.
Note: The DMA registers can only be written in supervisor mode. Some of them are also
Endinit-protected.
DMA_CHICRmx DMA Channel mx Interrupt Control
Register (m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 88
H
Page 12-81
DMA_
ADRCRmx
DMA Channel mx Address Control
Register (m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 8C
H
Page 12-83
DMA_SADRmx DMA Channel mx Source Address
Register (m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 90
H
Page 12-88
DMA_DADRmx DMA Channel mx Destination Address
Register (m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 94
H
Page 12-89
DMA_
SHADRmx
DMA Channel mx Shadow Address
Register (m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 98
H
Page 12-90
1) The absolute register address is calculated as follows:
Module Base Address (Table 12-5) + Offset Address (shown in this column)
Further, the following ranges for parameters m and x are valid: m = 0-1, x = 0-7
Table 12-6 Registers Overview - DMA Kernel Registers (cont’d)
Register Short
Name
Register Long Name Offset
Address
1)
Description
see
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