Infineon Technologies TC1796 - Page 707

TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-43 V2.0, 2007-07
DMA, V2.0
Table 12-6 Registers Overview - DMA Kernel Registers
Register Short
Name
Register Long Name Offset
Address
1)
Description
see
DMA_ID DMA Module Identification Register 008
H
Page 12-45
DMA_CHRSTR DMA Channel Reset Request Register 010
H
Page 12-51
DMA_TRSR DMA Transaction Request State
Register
014
H
Page 12-52
DMA_STREQ DMA Software Transaction Request
Register
018
H
Page 12-54
DMA_HTREQ DMA Hardware Transaction Request
Register
01C
H
Page 12-55
DMA_EER DMA Enable Error Register 020
H
Page 12-56
DMA_ERRSR DMA Error Status Register 024
H
Page 12-59
DMA_CLRE DMA Clear Error Register 028
H
Page 12-62
DMA_GINTR DMA Global Interrupt Set Register 02C
H
Page 12-50
DMA_MESR DMA Move Engine Status Register 030
H
Page 12-69
DMA_MEmR Move Engine m Read Register
(m = 0, 1)
34
H
+m× 4 Page 12-71
DMA_MEmPR Move Engine m Pattern Register
(m = 0,1)
3C
H
+m× 4 Page 12-72
DMA_
MEmAENR
Move Engine m Access Enable
Register (m = 0, 1)
44
H
+m× 8 Page 12-73
DMA_
MEmARR
Move Engine m Access Range
Register (m = 0, 1)
48
H
+m× 8 Page 12-74
DMA_INTSR DMA Interrupt Status Register 054
H
Page 12-64
DMA_INTCR DMA Interrupt Clear Register 058
H
Page 12-67
DMA_WRPSR DMA Wrap Status Register 05C
H
Page 12-66
DMA_OCDSR DMA OCDS Register 064
H
Page 12-46
DMA_SUSPMR DMA Suspend Mode Register 068
H
Page 12-48
DMA_CHSRmx DMA Channel mx Status Register
(m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 80
H
Page 12-80
DMA_CHCRmx DMA Channel mx Control Register
(m = 0-1, x = 0-7)
(m × 8+x)×
20
H
+ 84
H
Page 12-76