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Instruction Set
1073
SPNU563A–March 2018
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Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
The Sub-Opcode field C[25:3] determines which type of operation (ADD, ADC, AND, OR, SBB, SUB,
XOR) is executed by the instruction. A list of these operations and the corresponding Sub-Opcode
encoding can be found in Table 23-76.
All arithmetic is performed using 32-bit integer math. However, source and destination operands vary in
width and can be 9 bits (REMP), 25 bits (A, B) or 32 bits (R,S,T, IMM, REM). Source operands REMP,
A,B are extended to 32-bits before being operated on. Also the result of the computation needs to be
truncated before being written back to REMP, A, or B when these are selected as destination operands.
Table 23-77 provides a list of source operand options, how they are expanded to 32-bit integers (if
applicable) and the control field encoding to select the option for src1 and src2 operands.
Table 23-78 provides a similar list of destination operands and their encodings. Up to two destination
operands may be selected for each instruction, a register/immediate destination and a remote destination
may be selected simultaneously. Truncation is performed independently for each destination operand as
appropriate to its size.
An optional shift step following the arithmetic or logical operation may be selected through the smode and
scount operands. The shift or rotate type is selected by the smode field; Table 23-79 illustrates the options
that are available for smode. The number of bits shifted is determined by the scount operand.
Table 23-76. Arithmetic / Bitwise Logic Sub-Opcodes
Instruction Description Operation Sub-Opcode
ADC Add with Carry result = src1 + src2 + C C[25:23] = 011
ADD Add result = src1 + src2 C[25:23] = 001
AND Bitwise Logic And result = src1 & src2 C[25:23] = 010
OR Bitwise Logic Or result = src1 | src2 C[25:23] = 100
SBB Subtract with Borrow result = src1 - src2 - C C[25:23] = 110
SUB Subtract result = src1 - src2 C[25:23] = 101
XOR Bitwise Logic Exclusive Or result = src1 ^ src2 C[25:23] = 111
Table 23-77. Source Operand Choices
Source Operand 32-bit value Address src1 src2
A {A[24:0], 0x00} n/a C[22:19] = 0010 C[18:16] = 010
B {B[24:0], 0x00} n/a C[22:19] = 0011 C[18:16] = 011
R R[31:0] n/a C[22:19] = 0100 C[18:16] = 100
S S[31:0] n/a C[22:19] = 0101 C[18:16] = 101
T T[31:0] n/a C[22:19] = 0110 C[18:16] = 110
IMM D[31:0] current instruction address C[22:19] = 0001 C[18:16] = 001
ZERO 0x00000000 n/a C[22:19] = 0000 C[18:16] = 000
ONES 0xFFFFFFFF n/a C[22:19] = 0111 C[18:16] = 111
REM D[31:0] specified by remote[8:0] C[22:19] = 1000 n/a
REMP {0x000000, P[8:0]} specified by remote[8:0] C[22:19] = 1001 n/a
Table 23-78. Destination Operand Choices
Destination
Operand
Stored Value Address dest rdest
A A[24:0] = result [31:8] n/a C[7] = 0, C[2:1] = 00 n/a
B B[24:0] = result [31:8] n/a C[7] = 0, C[2:1] = 01 n/a
R R[24:0] = result [31:0] n/a C[7] = 1, C[2:1] = 00 n/a
S S[24:0] = result [31:0] n/a C[7] = 1, C[2:1] = 01 n/a
T T[24:0] = result [31:0] n/a C[7] = 0, C[2:1] = 10 n/a
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