Module Operation
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SPNU563A–March 2018
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FlexRay Module
26.2.1.1.1.6 Transfer Status Indication
There are 3 registers indicating the transfer status:
• Transfer Status Current Buffer (TSCB) shows the current transfer buffer status
• Last Transferred Buffer to Communication Controller (LTBCC) indicates the last completed buffer
transfer to the communication controller
• Last Transferred Buffer to System Memory (LTBSM) shows the last completed buffer transfer to
system memory
26.2.1.1.1.7 Transfer Mirror Function
In order to efficiently access the transfer unit status registers in the system memory, the following registers
can be mirrored to the system memory starting at the base address defined in the Base Address of
Mirrored Status (BAMS) register:
• Transfer Status Current Buffer (TSCB)
• Last Transferred Buffer to Communication Controller (LTBCC)
• Last Transferred Buffer to System Memory (LTBSM)
• Transfer to System Memory Occurred 1/2/3/4 (TSMO1-4)
• Transfer to Communication Controller Occurred 1/2/3/4 (TCCO1-4)
• Transfer Occurred OFFset (TOOFF)
The mirrored values are updated after completion of a buffer transfer.
The mirroring of these registers can be disabled if not needed.
Table 26-3. Mirroring Address Mapping
Address Register
BAMS+0x00 TSCB
BAMS+0x04 LTBCC
BAMS+0x08 LTBSM
BAMS+0x0C TSMO1
BAMS+0x10 TSMO2
BAMS+0x14 TSMO3
BAMS+0x18 TSMO4
BAMS+0x1C TCCO1
BAMS+0x20 TCCO2
BAMS+0x24 TCCO3
BAMS+0x28 TCCO4
BAMS+0x2C TOOFF
26.2.1.1.1.8 Endianness Correction
For the data transfer by the Transfer Unit an Endianness correction mechanism can be used to switch big
Endianness data to little Endianness data and vice versa.
For maximum flexibility, 6 bits are available in the Global Control Set/Reset Register (GCS/R) to control.
• Header Data byte-order
• Payload Data byte-order
• Byte-order of the FlexRay Core registers and the Transfer Configuration RAM data of the Transfer Unit
independently and in both directions.
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