GEN
CHK
CHK
GEN
GEN CHKECC Generator ECC Checker
CHK
CHK
Message
RAM
Transient
Buffer
RAM A
Transient
Buffer
RAM B
PRT A
PRT B
Output
Buffer
RAM 1,2
GEN
GEN
CHKGEN
Input
Buffer
RAM 1,2
Module Operation
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SPNU563A–March 2018
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FlexRay Module
An uncorrectable RAM error interrupt can be generated, if enabled by the UCRE bit in the error interrupt
enable register (EIES/R). For ECC single-bit error, the uncorrectable RAM error interrupt is only
generated, if the ECC single-bit error correction is disabled and the single-bit error indication key
(SBE_EVT_EN in ECC_CTRL) is enabled. When single-bit error correction is turned off, the ECC
algorithm will detect up to 3 bits in error in a word.
For ECC multi-bit errors the faulty message buffer number, together with the information of the failing
RAM, can be read from the message handler status (MHDS) register. Equivalent information is available
for ECC single-bit errors in the single-bit error location (SBESTAT) register, irrespective of ECC single-bit
error correction being enabled.
Figure 26-27 shows the data paths between the RAM blocks and the ECC generators and checkers.
The ECC generation is done according to the ECC syndrome tables as shown in Figure 26-28 and
Figure 26-29.
Figure 26-27. ECC Generation and Check
NOTE: The ECC generator and ECC checker are not part of the RAM blocks, but of the RAM
access logic.
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