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FlexRay Module Registers
1301
SPNU563A–March 2018
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FlexRay Module
Figure 26-62. Trigger Transfer to System Memory Set 3 (TTSMS3) [offset_TU = 90h]
31 16
TTSMS3[95-80]
R/WS-0
15 0
TTSMS3[79-64]
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 26-42. Trigger Transfer to System Memory Set 3 (TTSMS3) Field Descriptions
Bit Field Value Description
31-0 TTSMS3[n] Trigger Transfer to System Memory Set 3. The register bits 0 to 31 correspond to message buffers
64 to 95. Each bit of the register controls the message buffer transfer to the system memory in the
following manner (note that only the least-significant bit of all four combined TTSM registers will be
currently scheduled for transmission).
0 No transfer request.
1 Transfer based on address defined in TBA.
Figure 26-63. Trigger Transfer to System Memory Reset 3 (TTSMR3) [offset_TU = 94h]
31 16
TTSMR3
R/WC-0
15 0
TTSMR3
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-43. Trigger Transfer to System Memory Reset 3 (TTSMR3) Field Descriptions
Bit Field Description
31-0 TTSMR3 Trigger Transfer to System Memory Reset 3. The TTSMR3 register shows the identical values to TTSMS3 if
read.
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