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FlexRay Module Registers
1317
SPNU563A–March 2018
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FlexRay Module
Figure 26-94. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) [offset_TU = 110h]
31 16
TSMIES3[95-80]
R/WS-0
15 0
TSMIES3[79-64]
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 26-74. Transfer to System Memory Interrupt Enable Set 3 (TSMIES3) Field Descriptions
Bit Field Value Description
31-0 TSMIES3[n] Transfer to System Memory Interrupt Enable Set 3. The register bits 0 to 31 correspond to
message buffers 64 to 95. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO3 bit is set:
0 No interrupt.
1 Interrupt is generated.
Figure 26-95. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) [offset_TU = 114h]
31 16
TSMIER3
R/WC-0
15 0
TSMIER3
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-75. Transfer to System Memory Interrupt Enable Reset 3 (TSMIER3) Field Descriptions
Bit Field Description
31-0 TSMIER3 Transfer to System Memory Interrupt Enable Reset 3. The TSMIER3 register shows the identical values to
TSMIES3 if read.
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