FlexRay Module Registers
www.ti.com
1318
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
Figure 26-96. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) [offset_TU = 118h]
31 16
TSMIES4[127-112]
R/WS-0
15 0
TSMIES4[111-96]
R/WS-0
LEGEND: R/W = Read/Write; R = Read only; S = Set; -n = value after reset
Table 26-76. Transfer to System Memory Interrupt Enable Set 4 (TSMIES4) Field Descriptions
Bit Field Value Description
31-0 TSMIES4[n] Transfer to System Memory Interrupt Enable Set 4. The register bits 0 to 31 correspond to
message buffers 96 to 127. Each bit of the register enables a potential interrupt, which occurs if the
corresponding TSMO4 bit is set:
0 No interrupt.
1 Interrupt is generated.
Figure 26-97. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) [offset_TU = 11Ch]
31 16
TSMIER4
R/WC-0
15 0
TSMIER4
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Table 26-77. Transfer to System Memory Interrupt Enable Reset 4 (TSMIER4) Field Descriptions
Bit Field Description
31-0 TSMIER4 Transfer to System Memory Interrupt Enable Reset 4. The TSMIER4 register shows the identical values to
TSMIES4 if read.