FlexRay Module Registers
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SPNU563A–March 2018
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FlexRay Module
26.3.2.2.6 Status Interrupt Enable Set / Reset Register (SIES/SIER)
The settings in the status interrupt enable register determine which status changes in the status interrupt
register will result in an interrupt. The enable bits are set by writing to SIES (address 38h) and reset by
writing to SIER (address 3Ch). Writing 1 sets or resets the specific enable bit, writing 0 has no effect.
Figure 26-122 and Table 26-101 illustrate this register.
Figure 26-122. Status Interrupt Enable Set/Reset Register (SIES/SIER) [offset_CC = 38h/3Ch]
31 26 25 24 23 18 17 16
Reserved MTSBE WUPBE Reserved MTSAE WUPAE
R-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDSE MBSIE SUCSE SWEE TOBCE TIBCE TI1E TI0E NMVCE RFFE RFNEE RXIE TXIE CYCSE CASE WSTE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26-101. Status Interrupt Enable Set/Reset Register (SIES/SIER) Field Descriptions
Bit Field Value Description
31-26 Reserved 0 Reads return 0. Writes have no effect.
25 MTSBE MTS received on channel B interrupt enable.
0 Interrupt is disabled.
1 MTS received on channel B interrupt is enabled.
24 WUPBE Wakeup pattern channel B interrupt enable.
0 Interrupt is disabled.
1 Wakeup pattern channel B interrupt is enabled.
23-18 Reserved 0 Reads return 0. Writes have no effect.
17 MTSAE MTS received on channel A interrupt enable.
0 Interrupt is disabled.
1 MTS received on channel A interrupt is enabled.
16 WUPAE Wakeup pattern channel A interrupt enable.
0 Interrupt is disabled.
1 Wakeup pattern channel A interrupt is enabled.
15 SDSE Start of dynamic segment interrupt enable.
0 Interrupt is disabled.
1 Start of dynamic segment interrupt is enabled.
14 MBSIE Message buffer status interrupt enable.
0 Interrupt is disabled.
1 Message buffer status interrupt is enabled.
13 SUCSE Startup completed successfully interrupt enable.
0 Interrupt is disabled.
1 Startup completed successfully interrupt is enabled.
12 SWEE Stop watch event interrupt enable.
0 Interrupt is disabled.
1 Stop watch event interrupt is enabled.
11 TOBCE Transfer output buffer completed interrupt enable.
0 Interrupt is disabled.
1 Transfer output buffer completed interrupt is enabled.
10 TIBCE Transfer input buffer completed interrupt enable.
0 Interrupt is disabled.
1 Transfer input buffer completed interrupt is enabled.
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