FlexRay Module Registers
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SPNU563A–March 2018
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FlexRay Module
26.3.2.4.7 Sync Frame Status (SFS)
This register is reset when the Communication Controller leaves CONFIG state or enters STARTUP state.
Figure 26-152 and Table 26-131 illustrate this register.
Figure 26-152. Sync Frame Status Register (SFS) [offset_CC = 120h]
31 20 19 18 17 16
Reserved RCLR MRCS OCLR MOCS
R-0 R-0 R-0 R-0 R-0
15 12 11 8 7 4 3 0
VSBO VSBE VSAO VSAE
R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 26-131. Sync Frame Status Register (SFS) Field Descriptions
Bit Field Value Description
31-20 Reserved 0 Reads return 0. Writes have no effect.
19 RCLR Rate correction limit reached. The Rate Correction Limit Reached flag signals to the Host, that the rate
correction value has exceeded its limit as defined by GTUC10.MRC. The flag is updated by the
communication controller at start of offset correction phase.
0 Rate correction is below limit.
1 Rate correction limit is reached.
18 MRCS Missing rate correction signal. The missing rate correction signal signals to the host that no rate
correction can be performed because no pairs of even/odd sync frames were received. The flag is
updated by the communication controller at start of offset correction phase.
0 Rate correction signal is valid.
1 Missing rate correction signal.
17 OCLR Offset correction limit reached. The offset correction limit reached flag signals to the host that the offset
correction value has reached its limit as defined by GTUC10.MOC. The flag is updated by the
communication controller at start of offset correction phase.
0 Offset correction is below limit.
1 Offset correction limit is reached.
16 MOCS Missing offset correction signal. The missing offset correction signal signals to the host that no rate
correction can be performed because no pairs of even / odd sync frames were received. The flag is
updated by the communication controller at start of offset correction phase.
0 Offset correction signal is valid.
1 Missing offset correction signal.
15-12 VSBO 0-Fh Valid sync frames channel B, odd communication cycle. Holds the number of valid sync frames
received on channel B in the odd communication cycle. If transmission of sync frames is enabled by
SUCC1.TXSY, the value is incremented by 1. The value is updated during the NIT of each odd
communication cycle.
11-8 VSBE 0-Fh Valid synch frames channel B, even communication cycle. Holds the number of valid sync frames
received and transmitted on channel B in the even communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY, the value is incremented by 1. The value is updated during the NIT of
each even communication cycle.
7-4 VSAO 0-Fh Valid synch frames channel A, odd communication cycle. Holds the number of valid sync frames
received and transmitted on channel A in the odd communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY, the value is incremented by 1. The value is updated during the NIT of
each odd communication cycle.
3-0 VSAE 0-Fh Valid synch frames channel A, even communication cycle. Holds the number of valid sync frames
received and transmitted on channel A in the even communication cycle. If transmission of sync frames
is enabled by SUCC1.TXSY, the value is incremented by 1. The value is updated during the NIT of
each even communication cycle.
NOTE: The bit fields VSBO, VSBE, VSAO, VSAE are only valid if the respective channel is
assigned to the communication controller by SUCC1.CCHA or SUCC1.CCHB.
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