ECC bits Data bits
TXBUF5
06
BASE+014h
Memory Organization During Normal Mode
00000000
31
00000000
ECC
BASE+ 400h + 014h
000000000
ECC-bits Organization During Test Mode
24 23
1615
7 6
0
031
Parity\ECC Memory
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SPNU563A–March 2018
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Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
28.5.2 Example of ECC Memory Organization
Suppose TXBUF5 (6th location in TXRAM portion) in the multi-buffer RAM is written with a value of
A001_AA55, then the corresponding ECC-bits will be updated in ECC location.
The ECC bits can be accessed by user, when Memory Test mode is enabled and additionally diagnostic
mode is also enabled. The actual ECC bits will be aligned as shown in Figure 28-93.
Figure 28-93. Example of ECC Bit Locations During Test Mode
NOTE: Access to ECC locations
ECC locations can be read/write only when Parity Memory Test mode and diagnostic mode
is enabled
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