SCI/LIN Control Registers
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
Table 29-19. SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions (continued)
Bit Field Value Description
6 CLR TOAWUS INT LVL Clear timeout after wakeup signal interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
5 Reserved 0 Reads return 0. Writes have no effect.
4 CLR TIMEOUT INT LVL Clear timeout interrupt. This bit is effective in LIN mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
3-2 Reserved 0 Reads return 0. Writes have no effect.
1 CLR WAKEUP INT LVL Clear wake-up interrupt. This bit is effective in LIN or SCI-compatible mode.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
0 CLR BRKDT INT LVL Clear break-detect interrupt. This bit is effective in SCI-compatible mode only.
0 Read: The interrupt level is mapped to the INT0 line.
Write: No effect.
1 Read: The interrupt level is mapped to the INT1 line.
Write: The interrupt level is mapped to the INT0 line.
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