SCI/LIN Control Registers
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SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7.15 SCI Pin I/O Control Register 1 (SCIPIO1)
Figure 29-44 and Table 29-30 illustrate this register.
Figure 29-44. SCI Pin I/O Control Register 1 (SCIPIO1) (offset = 40h)
31 8
Reserved
R-0
7 3 2 1 0
Reserved TX DIR RX DIR Reserved
R-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29-30. SCI Pin I/O Control Register 1 (SCIPIO1) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reads return 0. Writes have no effect.
2 TX DIR Transmit pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on
the LINTX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0). See Table 29-31
for the LINTX pin control with this bit and others.
0 LINTX is a general-purpose input pin.
1 LINTX is a general-purpose output pin.
1 RX DIR Receive pin direction. This bit is effective in LIN or SCI mode. This bit determines the data direction on
the LINRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0). See Table 29-32
for the LINRX pin control with this bit and others.
0 LINRX is a general-purpose input pin.
1 LINRX is a general-purpose output pin.
0 Reserved 0 Writes have no effect.
(1)
TX IN is a read-only bit. Its value always reflects the level of the SCITX pin.
Table 29-31. LINTX Pin Control
Function TX IN
(1)
TX OUT TX FUNC TX DIR
LINTX X X 1 X
General purpose input X X 0 0
General purpose output, high X 1 0 1
General purpose output, low X 0 0 1
(1)
RX IN is a read-only bit. Its value always reflects the level of the SCIRX pin.
Table 29-32. LINRX Pin Control
Function RX IN
(1)
RX OUT RX FUNC RX DIR
LINRX X X 1 X
General purpose input X X 0 0
General purpose output, high X 1 0 1
General purpose output, low X 0 0 1
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