Texas Instruments TMS570LC4357 - Page 1704

SCI/LIN Control Registers www.ti.com
1704
SPNU563A–March 2018
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Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7.19 SCI Pin I/O Control Register 5 (SCIPIO5)
Figure 29-48 and Table 29-36 illustrate this register.
Figure 29-48. SCI Pin I/O Control Register 5 (SCIPIO5) (offset = 50h)
31 8
Reserved
R-0
7 3 2 1 0
Reserved TX CLR RX CLR Reserved
R-0 R/W-0 R/W-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29-36. SCI Pin I/O Control Register 5 (SCIPIO5) Field Descriptions
Bit Field Value Description
31-3 Reserved 0 Reads return 0. Writes have no effect.
2 TX CLR Transmit pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin
LINTX if the following conditions are met:
• TX FUNC = 0 (LINTX pin is a general-purpose I/O.)
• TX DIR = 1 (LINTX pin is a general-purpose output.)
0 Read: The output on LINTX is at logic low (0).
Write: No effect.
1 Read: The output on LINTX is at logic high (1).
Write: The output on LINTX is at logic low (0).
1 RX CLR Receive pin clear. This bit is effective in LIN or SCI mode. This bit clears the logic to be output on pin
LINRX if the following conditions are met:
• RX FUNC = 0 (LINRX pin is a general-purpose I/O.)
• RX DIR = 1 (LINRX pin is a general-purpose output.)
0 Read: The output on LINRX is at logic low (0).
Write: No effect.
1 Read: The output on LINRX is at logic high (1).
Write: The output on LINRX is at logic low (0).
0 Reserved 0 Reads return 0. Writes have no effect.