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SPNU563A–March 2018
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EMAC/MDIO Module
32.3.11 EMAC Control Module Miscellaneous Interrupt Status Registers (C0MISCSTAT)
The EMAC control module miscellaneous interrupt status register (C0MISCSTAT) is shown in Figure 32-
25 and described in Table 32-21
Figure 32-25. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT)
(offset = 4Ch)
31 16
Reserved
R-0
15 4 3 2 1 0
Reserved STATPEND
STAT
HOSTPEND
STAT
LINKINT0
STAT
USERINT0
STAT
R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 32-21. EMAC Control Module Miscellaneous Interrupt Status Register (C0MISCSTAT)
Bit Field Value Description
31-4 Reserved 0 Reserved
3 STATPENDSTAT Interrupt status for EMAC STATPEND masked by the C0MISCEN register.
0 EMAC STATPEND does not satisfy conditions to generate a C0MISCPULSE interrupt.
1 EMAC STATPEND satisfies conditions to generate a C0MISCPULSE interrupt.
2 HOSTPENDSTAT Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register.
0 EMAC HOSTPEND does not satisfy conditions to generate a C0MISCPULSE interrupt.
1 EMAC HOSTPEND satisfies conditions to generate a C0MISCPULSE interrupt.
1 LINKINT0STAT Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register.
0 MDIO LINKINT0 does not satisfy conditions to generate a C0MISCPULSE interrupt.
1 MDIO LINKINT0 satisfies conditions to generate a C0MISCPULSE interrupt.
0 USERINT0STAT Interrupt status for MDIO USERINT0 masked by the C0MISCEN register.
0 MDIO USERINT0 does not satisfy conditions to generate a C0MISCPULSE interrupt.
1 MDIO USERINT0 satisfies conditions to generate a C0MISCPULSE interrupt.