Texas Instruments TMS570LC4357 - Page 1863

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SPNU563A–March 2018
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EMAC/MDIO Module
32.3.10 EMAC Control Module Transmit Interrupt Status Registers (C0TXSTAT)
The EMAC control module transmit interrupt status register (C0TXSTAT) is shown in Figure 32-24 and
described in Table 32-20
Figure 32-24. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT) (offset = 48h)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
TXCH7STAT TXCH6STAT TXCH5STAT TXCH4STAT TXCH3STAT TXCH2STAT TXCH1STAT TXCH0STAT
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 32-20. EMAC Control Module Transmit Interrupt Status Register (C0TXSTAT)
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TXCH7STAT Interrupt status for TX Channel 7 masked by the C0TXEN register.
0 TX Channel 7 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 7 satisfies conditions to generate a C0TXPULSE interrupt.
6 TXCH6STAT Interrupt status for TX Channel 6 masked by the C0TXEN register.
0 TX Channel 6 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 6 satisfies conditions to generate a C0TXPULSE interrupt.
5 TXCH5STAT Interrupt status for TX Channel 5 masked by the C0TXEN register.
0 TX Channel 5 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 5 satisfies conditions to generate a C0TXPULSE interrupt.
4 TXCH4STAT Interrupt status for TX Channel 4 masked by the C0TXEN register.
0 TX Channel 4 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 4 satisfies conditions to generate a C0TXPULSE interrupt.
3 TXCH3STAT Interrupt status for TX Channel 3 masked by the C0TXEN register.
0 TX Channel 3 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 3 satisfies conditions to generate a C0TXPULSE interrupt.
2 TXCH2STAT Interrupt status for TX Channel 2 masked by the C0TXEN register.
0 TX Channel 2 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 2 satisfies conditions to generate a C0TXPULSE interrupt.
1 TXCH1STAT Interrupt status for TX Channel 1 masked by the C0TXEN register.
0 TX Channel 1 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 1 satisfies conditions to generate a C0TXPULSE interrupt.
0 TXCH0STAT Interrupt status for TX Channel 0 masked by the C0TXEN register.
0 TX Channel 0 does not satisfy conditions to generate a C0TXPULSE interrupt.
1 TX Channel 0 satisfies conditions to generate a C0TXPULSE interrupt.