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EMAC Module Registers www.ti.com
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SPNU563A–March 2018
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EMAC/MDIO Module
32.5.46 Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)
The transmit channel 0-7 DMA head descriptor pointer register (TX nHDP) is shown in Figure 32-87 and
described in Table 32-85.
Figure 32-87. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
(offset = 600h-61Ch)
31 0
TXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 32-85. Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP)
Field Descriptions
Bit Field Description
31-0 TXnHDP Transmit channel n DMA Head Descriptor pointer. Writing a transmit DMA buffer descriptor address to a head
pointer location initiates transmit DMA operations in the queue for the selected channel. Writing to these
locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0
on reset.
32.5.47 Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP)
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 32-88 and
described in Table 32-86.
Figure 32-88. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
(offset = 620h-63Ch)
31 0
RXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 32-86. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
Field Descriptions
Bit Field Description
31-0 RXnHDP Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor address to this
location allows receive DMA operations in the selected channel when a channel frame is received. Writing to
these locations when they are nonzero is an error (except at reset). Host software must initialize these
locations to 0 on reset.