Texas Instruments TMS570LC4357

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2119
SPNU563A–March 2018
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Data Modification Module (DMM)
Table 36-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued)
Bit Field Value Description
14 DEST3REG1 Destination 3 Region 1 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 3 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
13 DEST2REG2 Destination 2 Region 2 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 2 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
12 DEST2REG1 Destination 2 Region 1 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 2 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
11 DEST1REG2 Destination 1 Region 2 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 1 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
10 DEST1REG1 Destination 1 Region 1 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 1 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
9 DEST0REG2 Destination 0 Region 2 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 0 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).