Texas Instruments TMS570LC4357

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SPNU563A–March 2018
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Data Modification Module (DMM)
36.3.2 DMM Interrupt Set Register (DMMINTSET)
This register contains the interrupt set bits for error interrupts and functional interrupts. Only the bits which
are relevant for the particular mode (trace mode or direct data mode) will be taken into account for the
interrupt generation.
Figure 36-8. DMM Interrupt Set Register (DMMINTSET) [offset = 04h]
31 24
Reserved
R-0
23 18 17 16
Reserved PROG_BUFF EO_BUFF
R-0 R/WP-0 R/WP-0
15 14 13 12 11 10 9 8
DEST3REG2 DEST3REG1 DEST2REG2 DEST2REG1 DEST1REG2 DEST1REG1 DEST0REG2 DEST0REG1
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
7 6 5 4 3 2 1 0
BUSERROR BUFF_OVF SRC_OVF DEST3_ERR DEST2_ERR DEST1_ERR DEST0_ERR PACKET_
ERR_INT
R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0 R/WP-0
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privileged mode only; -n = value after reset
Table 36-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions
Bit Field Value Description
31-18 Reserved 0 Reads returns 0. Writes have no effect.
17 PROG_BUFF Programmable Buffer Interrupt Set. This enables the interrupt generation in case the buffer
pointer equals the programmed value in the DMMINTPT register (Section 36.3.11). This bit is
only relevant in Direct Data Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on pointer match.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
16 EO_BUFF End of Buffer Interrupt Set. This enables the interrupt generation in case data was written to
the last entry in the buffer and the pointer wrapped around to the beginning of the buffer. This
bit is only relevant in Direct Data Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on writing to the last entry.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
15 DEST3REG2 Destination 3 Region 2 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 3 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).