Texas Instruments TMS570LC4357

Control Registers www.ti.com
2120
SPNU563A–March 2018
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
Data Modification Module (DMM)
Table 36-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued)
Bit Field Value Description
8 DEST0REG1 Destination 0 Region 1 Interrupt Set. This enables the interrupt generation in case data was
accessed at the start address of Destination 0 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated
1 An interrupt will be generated on a write to the start address of this region
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
7 BUSERROR Bus Error Response for errors generated when doing internal bus transfers.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
6 BUFF_OVF Buffer Overflow. This enables the interrupt generation in case new data is received, while the
previous data still has not been transmitted.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
5 SRC_OVF Source Overflow. This enables an interrupt if the external system experienced and overflow
that was signaled in the Trace Mode packet.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
4 DEST3_ERR Destination 3 Error. This enables the interrupt generation in case data should be written into a
address not specified by DMMDEST3REG1/DMMDEST3BL1 or
DMMDEST3REG2/DMMDEST3BL2. If both blocksizes are programmed to 0 or a reserved
value, the interrupt will still be generated, the write to the internal RAM however will not take
place.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).