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Control Registers
2121
SPNU563A–March 2018
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Data Modification Module (DMM)
Table 36-8. DMM Interrupt Set Register (DMMINTSET) Field Descriptions (continued)
Bit Field Value Description
3 DEST2_ERR Destination 2 Error Interrupt Set. This enables the interrupt generation in case data should be
written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or
DMMDEST2REG2/DMMDEST2BL2. If both blocksizes are programmed to 0 or a reserved
value, the interrupt will still be generated, the write to the internal RAM however will not take
place.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
2 DEST1_ERR Destination 1 Error Interrupt Set. This enables the interrupt generation in case data should be
written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or
DMMDEST1REG2/DMMDEST1BL2. If both blocksizes are programmed to 0 or a reserved
value, the interrupt will still be generated, the write to the internal RAM however will not take
place.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
1 DEST0_ERR Destination 0 Error Interrupt Set. This enables the interrupt generation in case data should be
written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or
DMMDEST0REG2/DMMDEST0BL2. If both blocksizes are programmed to 0 or a reserved
value, the interrupt will still be generated, the write to the internal RAM however will not take
place.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
0 PACKET_ERR_INT Packet Error. This enables the interrupt generation in case of an error condition in the packet
reception. Please refer to Section 36.2.3 for the error conditions.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Enable interrupt (sets corresponding bit in DMMINTCLR; DMMINTLVL).
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