Texas Instruments TMS570LC4357

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2123
SPNU563A–March 2018
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Data Modification Module (DMM)
Table 36-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued)
Bit Field Value Description
15 DEST3REG2 Destination 3 Region 2 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 3 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
14 DEST3REG1 Destination 3 Region 1 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 3 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
13 DEST2REG2 Destination 2 Region 2 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 2 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
12 DEST2REG1 Destination 2 Region 1 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 2 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
11 DEST1REG2 Destination 1 Region 2 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 1 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).