Texas Instruments TMS570LC4357

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SPNU563A–March 2018
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Data Modification Module (DMM)
Table 36-9. DMM Interrupt Clear Register (DMMINTCLR) Field Descriptions (continued)
Bit Field Value Description
10 DEST1REG1 Destination 1 Region 1 Interrupt Set.This enables the interrupt generation in case data was
accessed at the start address of Destination 1 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
9 DEST0REG2 Destination 0 Region 2 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 0 Region 2. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
8 DEST0REG1 Destination 0 Region 1 Interrupt Set.This disables the interrupt generation in case data was
accessed at the start address of Destination 0 Region 1. This bit is only relevant in Trace Mode.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated on a write to the start address of this region.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
7 BUSERROR Bus Error Response for errors generated when doing internal bus transfers.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).
6 BUFF_OVF Buffer Overflow.This disables the interrupt generation in case new data is received, while the
previous data still has not been transmitted.
User and privilege mode (read):
0 No interrupt will be generated.
1 An interrupt will be generated.
Privilege mode (write):
0 No influence on bit.
1 Disable interrupt (clears corresponding bit in DMMINTCLR; DMM Interrupt Level Register
(DMMINTLVL)).