Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.18 DMA Request Assignment Register 5 (DREQASI5)
Figure 20-36. DMA Request Assignment Register 5 (DREQASI5) [offset = 68h]
31 30 29 24 23 22 21 16
Reserved CH20ASI Reserved CH21ASI
R-0 R/WP-14h R-0 R/WP-15h
15 14 13 8 7 6 5 0
Reserved CH22ASI Reserved CH23ASI
R-0 R/WP-16h R-0 R/WP-17h
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-26. DMA Request Assignment Register 5 (DREQASI5) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH20ASI Channel 20 assignment. This bit field chooses the DMA request assignment for channel 20.
0 DMA request line 0 triggers channel 20.
: :
2Fh DMA request line 47 triggers channel 20.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-26 CH21ASI Channel 21 assignment. This bit field chooses the DMA request assignment for channel 21.
0 DMA request line 0 triggers channel 21.
: :
2Fh DMA request line 47 triggers channel 21.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH22ASI Channel 22 assignment. This bit field chooses the DMA request assignment for channel 22.
0 DMA request line 0 triggers channel 22.
: :
2Fh DMA request line 47 triggers channel 22.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH23ASI Channel 23 assignment. This bit field chooses the DMA request assignment for channel 23.
0 DMA request line 0 triggers channel 23.
: :
2Fh DMA request line 47 triggers channel 23.
30h-
3Fh
Reserved
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