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Control Registers and Control Packets
737
SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.19 DMA Request Assignment Register 6 (DREQASI6)
Figure 20-37. DMA Request Assignment Register 6 (DREQASI6) [offset = 6Ch]
31 30 29 24 23 22 21 16
Reserved CH24ASI Reserved CH25ASI
R-0 R/WP-18h R-0 R/WP-19h
15 14 13 8 7 6 5 0
Reserved CH26ASI Reserved CH27ASI
R-0 R/WP-1Ah R-0 R/WP-1Bh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-27. DMA Request Assignment Register 6 (DREQASI6) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH24ASI Channel 24 assignment. This bit field chooses the DMA request assignment for channel 24.
0 DMA request line 0 triggers channel 24.
: :
2Fh DMA request line 47 triggers channel 24.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-16 CH25ASI Channel 25 assignment. This bit field chooses the DMA request assignment for channel 25.
0 DMA request line 0 triggers channel 25.
: :
2Fh DMA request line 47 triggers channel 25.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH26ASI Channel 26 assignment. This bit field chooses the DMA request assignment for channel 26.
0 DMA request line 0 triggers channel 26.
: :
2Fh DMA request line 47 triggers channel 26.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH27ASI Channel 27 assignment. This bit field chooses the DMA request assignment for channel 27.
0 DMA request line 0 triggers channel 27.
: :
2Fh DMA request line 47 triggers channel 27.
30h-
3Fh
Reserved