Control Registers and Control Packets
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SPNU563A–March 2018
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Direct Memory Access Controller (DMA) Module
20.3.1.20 DMA Request Assignment Register 7 (DREQASI7)
Figure 20-38. DMA Request Assignment Register 7 (DREQASI7) [offset = 70h]
31 30 29 24 23 22 21 16
Reserved CH28ASI Reserved CH29ASI
R-0 R/WP-1Ch R-0 R/WP-1Dh
15 14 13 8 7 6 5 0
Reserved CH30ASI Reserved CH31ASI
R-0 R/WP-1Eh R-0 R/WP-1Fh
LEGEND: R/W = Read/Write; R = Read only; WP = Write in privilege mode only; -n = value after reset
Table 20-28. DMA Request Assignment Register 7 (DREQASI7) Field Descriptions
Bit Field Value Description
31-30 Reserved 0 Reads return 0. Writes have no effect.
29-24 CH28ASI Channel 28 assignment. This bit field chooses the DMA request assignment for channel 28.
0 DMA request line 0 triggers channel 28.
: :
2Fh DMA request line 47 triggers channel 28.
30h-
3Fh
Reserved
23-22 Reserved 0 Reads return 0. Writes have no effect.
21-16 CH29ASI Channel 29 assignment. This bit field chooses the DMA request assignment for channel 29.
0 DMA request line 0 triggers channel 29.
: :
2Fh DMA request line 47 triggers channel 29.
30h-
3Fh
Reserved
15-14 Reserved 0 Reads return 0. Writes have no effect.
13-8 CH30ASI Channel 30 assignment. This bit field chooses the DMA request assignment for channel 30.
0 DMA request line 0 triggers channel 30.
: :
2Fh DMA request line 47 triggers channel 30.
30h-
3Fh
Reserved
7-6 Reserved 0 Reads return 0. Writes have no effect.
5-0 CH31ASI Channel 31 assignment. This bit field chooses the DMA request assignment for channel 31.
0 DMA request line 0 triggers channel 31.
: :
2Fh DMA request line 47 triggers channel 31.
30h-
3Fh
Reserved
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