Texas Instruments TMS570LC4357 - Page 78

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SPNU563A–March 2018
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List of Tables
10-16. CORE1 Current MISR Register (CORE1_CURMISRn) Field Descriptions ....................................... 453
10-17. CORE2 Current MISR Register (CORE2_CURMISRn) Field Descriptions ....................................... 454
10-18. Signature Compare Self-Check Regsiter (STCSCSCR) Field Descriptions ...................................... 455
10-19. STC Current ROM Address Register (STCCADDR2) Field Descriptions ......................................... 455
10-20. STC Clock Prescalar Register (STCCLKDIV) Field Descriptions .................................................. 456
10-21. Segment Interval Preload Register (STCSEGPLR) Field Descriptions............................................ 457
11-1. NMPU Region............................................................................................................. 461
11-2. Access Permission ....................................................................................................... 463
11-3. NMPU Registers .......................................................................................................... 471
11-4. MPU Revision ID Register (MPUREV) Field Descriptions .......................................................... 472
11-5. MPU Lock Register (MPULOCK) Field Descriptions................................................................. 472
11-6. MPU Diagnostics Control Register (MPUDIAGCTRL) Field Descriptions......................................... 473
11-7. MPU Diagnostic Address Register (MPUDIAGADDR) Field Descriptions ........................................ 474
11-8. MPU Error Status Register (MPUERRSTAT) Field Descriptions................................................... 474
11-9. MPU Error Address Register (MPUERRADDR) Field Descriptions................................................ 476
11-10. MPU Control Register 1 (MPUCTRL1) Field Descriptions .......................................................... 476
11-11. MPU Control Register 2 (MPUCTRL2) Field Descriptions .......................................................... 477
11-12. MPU Type Register (MPUTYPE) Field Descriptions................................................................. 478
11-13. MPU Region Base Address Register (MPUREGBASE) Field Descriptions ...................................... 479
11-14. MPU Region Size and Enable Register (MPUREGSENA) Field Descriptions ................................... 479
11-15. MPU Region Access Control Register (MPUREGACR) Field Descriptions....................................... 481
11-16. MPU Region Number Register (MPUREGNUM) Field Descriptions............................................... 482
12-1. EPC Control Registers ................................................................................................... 488
12-2. EPC REVID Register (EPCREVID) Field Descriptions .............................................................. 489
12-3. EPC Control Register (EPCCNTRL) Field Descriptions............................................................. 490
12-4. Uncorrectable Error Status Register (UERRSTAT) Field Descriptions............................................ 491
12-5. EPC Error Status Register (EPCERRSTAT) Field Descriptions.................................................... 492
12-6. FIFO Full Status Register (FIFOFULLSTAT) Field Descriptions ................................................... 493
12-7. IP Interface FIFO Overflow Status Register (OVRFLWSTAT) Field Descriptions ............................... 494
12-8. CAM Index Available Status Register (CAMAVAILSTAT) Field Descriptions .................................... 494
12-9. Uncorrectable Error Address Register n (UERR_ADDR) Field Descriptions ..................................... 495
12-10. CAM Content Update Register n (CAM_CONTENT) Field Descriptions.......................................... 495
12-11. CAM Index Registers (CAM_INDEXn) Field Descriptions........................................................... 496
12-12. CAM Index Register n.................................................................................................... 496
13-1. Compare Match Test Sequence ........................................................................................ 501
13-2. CPU / VIM Compare Mismatch Test Sequence ...................................................................... 502
13-3. Error Flags and Error Signals Generation in Each Mode............................................................ 503
13-4. CPU1 (Main CPU) Signals Being Inverted Before Being Compared .............................................. 504
13-5. Checker CPU Signals to Monitor ....................................................................................... 505
13-6. Checker CPU Inactivity Monitor Compare Mismatch Test .......................................................... 506
13-7. Control Registers ......................................................................................................... 507
13-8. CCM-R5F Status Register 1 (CCMSR1) Field Descriptions ........................................................ 508
13-9. CCM-R5F Key Register 1 (CCMKEYR1) Field Descriptions........................................................ 509
13-10. CCM-R5F Status Register 2 (CCMSR2) Field Descriptions ........................................................ 510
13-11. CCM-R5F Key Register 2 (CCMKEYR2) Field Descriptions........................................................ 511
13-12. CCM-R5F Status Register 3 (CCMSR3) Field Descriptions ........................................................ 512
13-13. CCM-R5F Key Register 2 (CCMKEYR2) Field Descriptions........................................................ 513
13-14. CCM-R5F Polarity Control Register (CCMPOLCNTRL) Field Descriptions....................................... 513
13-15. CCM-R5F Status Register 4 (CCMSR4) Field Descriptions ........................................................ 514