Texas Instruments TMS570LC4357 - Page 79

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SPNU563A–March 2018
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List of Tables
13-16. CCM-R5F Key Register 4 (CCMKEYR4) Field Descriptions........................................................ 515
13-17. CCM-R5FPower Domain Status Register 0 (CCMPDSTAT0) Field Descriptions................................ 516
14-1. Valid Frequency Ranges for PLL ....................................................................................... 525
14-2. PLL Value Encoding...................................................................................................... 526
14-3. Summary of PLL Timings................................................................................................ 530
14-4. PLL Module Registers.................................................................................................... 534
14-5. LPOCLKDET Module Registers ........................................................................................ 534
14-6. SSW PLL BIST Control Register 1 (SSWPLL1) Field Descriptions................................................ 535
14-7. SSW PLL BIST Control Register 2 (SSWPLL2) Field Descriptions................................................ 536
14-8. SSW PLL BIST Control Register 3 (SSWPLL3) Field Descriptions................................................ 537
15-1. DCC Control Registers .................................................................................................. 549
15-2. DCC Global Control Register (DCCGCTRL) Field Descriptions ................................................... 550
15-3. DCC Revision Id Register (DCCREV) Field Descriptions .......................................................... 551
15-4. DCC Counter0 Seed Register (DCCCNT0SEED) Field Descriptions ............................................. 551
15-5. DCC Valid0 Seed Register (DCCVALID0SEED) Field Descriptions .............................................. 552
15-6. DCC Counter1 Seed Register (DCCCNT0SEED) Field Descriptions ............................................. 552
15-7. DCC Status Register (DCCSTAT) Field Descriptions ............................................................... 553
15-8. DCC Counter0 Value Register (DCCCNT0) Field Descriptions ................................................... 554
15-9. DCC Valid0 Value Register (DCCVALID0) Field Descriptions ..................................................... 555
15-10. DCC Counter1 Value Register (DCCCNT1) Field Descriptions ................................................... 555
15-11. DCC Counter1 Clock Source Selection Register (DCCCNT1CLKSRC) Field Descriptions ................... 556
15-12. DCC Counter0 Clock Source Selection Register (DCCCNT0CLKSRC) Field Descriptions ................... 557
16-1. ESM Interrupt and ERROR Pin Behavior.............................................................................. 560
16-2. ESM Control Registers................................................................................................... 565
16-3. ESM Enable ERROR Pin Action/Response Register 1 (ESMEEPAPR1) Field Descriptions .................. 566
16-4. ESM Disable ERROR Pin Action/Response Register 1 (ESMDEPAPR1) Field Descriptions.................. 566
16-5. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) Field Descriptions ................................... 567
16-6. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) Field Descriptions................................. 567
16-7. ESM Interrupt Level Set/Status Register 1 (ESMILSR1) Field Descriptions...................................... 568
16-8. ESM Interrupt Level Clear/Status Register 1 (ESMILCR1) Field Descriptions ................................... 568
16-9. ESM Status Register 1 (ESMSR1) Field Descriptions .............................................................. 569
16-10. ESM Status Register 2 (ESMSR2) Field Descriptions .............................................................. 569
16-11. ESM Status Register 3 (ESMSR3) Field Descriptions .............................................................. 570
16-12. ESM ERROR Pin Status Register (ESMEPSR) Field Descriptions................................................ 570
16-13. ESM Interrupt Offset High Register (ESMIOFFHR) Field Descriptions............................................ 571
16-14. ESM Interrupt Offset Low Register (ESMIOFFLR) Field Descriptions............................................. 572
16-15. ESM Low-Time Counter Register (ESMLTCR) Field Descriptions................................................. 573
16-16. ESM Low-Time Counter Preload Register (ESMLTCPR) Field Descriptions..................................... 573
16-17. ESM Error Key Register (ESMEKR) Field Descriptions ............................................................. 574
16-18. ESM Status Shadow Register 2 (ESMSSR2) Field Descriptions .................................................. 574
16-19. ESM Influence ERROR Pin Set/Status Register 4 (ESMIEPSR4) Field Descriptions........................... 575
16-20. ESM Influence ERROR Pin Clear/Status Register 4 (ESMIEPCR4) Field Descriptions ........................ 575
16-21. ESM Interrupt Enable Set/Status Register 4 (ESMIESR4) Field Descriptions ................................... 576
16-22. ESM Interrupt Enable Clear/Status Register 4 (ESMIECR4) Field Descriptions................................. 576
16-23. ESM Interrupt Level Set/Status Register 4 (ESMILSR4) Field Descriptions...................................... 577
16-24. ESM Interrupt Level Clear/Status Register 4 (ESMILCR4) Field Descriptions ................................... 577
16-25. ESM Status Register 4 (ESMSR4) Field Descriptions............................................................... 578
16-26. ESM Influence ERROR Pin Set/Status Register 7 (ESMIEPSR7) Field Descriptions........................... 579
16-27. ESM Influence ERROR Pin Clear/Status Register 7 (ESMIEPCR7) Field Descriptions ........................ 579