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Texas Instruments TMS570LC4357 - Page 80

Texas Instruments TMS570LC4357
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80
SPNU563AMarch 2018
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Copyright © 2018, Texas Instruments Incorporated
List of Tables
16-28. ESM Interrupt Enable Set/Status Register 7 (ESMIESR7) Field Descriptions ................................... 580
16-29. ESM Interrupt Enable Clear/Status Register 7 (ESMIECR7) Field Descriptions................................. 580
16-30. ESM Interrupt Level Set/Status Register 7 (ESMILSR7) Field Descriptions...................................... 581
16-31. ESM Interrupt Level Clear/Status Register 7 (ESMILCR7) Field Descriptions ................................... 581
16-32. ESM Status Register 7 (ESMSR7) Field Descriptions............................................................... 582
17-1. RTI Registers.............................................................................................................. 595
17-2. RTI Global Control Register (RTIGCTRL) Field Descriptions....................................................... 596
17-3. RTI Timebase Control Register (RTITBCTRL) Field Descriptions ................................................. 597
17-4. RTI Capture Control Register (RTICAPCTRL) Field Descriptions ................................................. 598
17-5. RTI Compare Control Register (RTICOMPCTRL) Field Descriptions ............................................. 599
17-6. RTI Free Running Counter 0 Register (RTIFRC0) Field Descriptions............................................. 600
17-7. RTI Up Counter 0 Register (RTIUC0) Field Descriptions ........................................................... 600
17-8. RTI Compare Up Counter 0 Register (RTICPUC0) Field Descriptions............................................ 601
17-9. RTI Capture Free Running Counter 0 Register (RTICAFRC0) Field Descriptions............................... 601
17-10. RTI Capture Up Counter 0 Register (RTICAUC0) Field Descriptions ............................................. 602
17-11. RTI Free Running Counter 1 Register (RTIFRC1) Field Descriptions............................................. 602
17-12. RTI Up Counter 1 Register (RTIUC1) Field Descriptions ........................................................... 603
17-13. RTI Compare Up Counter 1 Register (RTICPUC1) Field Descriptions............................................ 604
17-14. RTI Capture Free Running Counter 1 Register (RTICAFRC1) Field Descriptions............................... 605
17-15. RTI Capture Up Counter 1 Register (RTICAUC1) Field Descriptions ............................................. 605
17-16. RTI Compare 0 Register (RTICOMP0) Field Descriptions .......................................................... 606
17-17. RTI Update Compare 0 Register (RTIUDCP0) Field Descriptions ................................................. 606
17-18. RTI Compare 1 Register (RTICOMP1) Field Descriptions .......................................................... 607
17-19. RTI Update Compare 1 Register (RTIUDCP1) Field Descriptions ................................................. 607
17-20. RTI Compare 2 Register (RTICOMP2) Field Descriptions .......................................................... 608
17-21. RTI Update Compare 2 Register (RTIUDCP2) Field Descriptions ................................................. 608
17-22. RTI Compare 3 Register (RTICOMP3) Field Descriptions .......................................................... 609
17-23. RTI Update Compare 3 Register (RTIUDCP3) Field Descriptions ................................................. 609
17-24. RTI Timebase Low Compare Register (RTITBLCOMP) Field Descriptions ...................................... 610
17-25. RTI Timebase High Compare Register (RTITBHCOMP) Field Descriptions ..................................... 610
17-26. RTI Set Interrupt Control Register (RTISETINTENA) Field Descriptions ......................................... 611
17-27. RTI Clear Interrupt Control Register (RTICLEARINTENA) Field Descriptions ................................... 613
17-28. RTI Interrupt Flag Register (RTIINTFLAG) Field Descriptions...................................................... 615
17-29. Digital Watchdog Control Register (RTIDWDCTRL) Field Descriptions........................................... 616
17-30. Digital Watchdog Preload Register (RTIDWDPRLD) Field Descriptions .......................................... 617
17-31. Watchdog Status Register (RTIWDSTATUS) Field Descriptions .................................................. 618
17-32. RTI Watchdog Key Register (RTIDWDKEY) Field Descriptions.................................................... 619
17-33. Example of a WDKEY Sequence....................................................................................... 619
17-34. RTI Watchdog Down Counter Register (RTIDWDCNTR) Field Descriptions..................................... 620
17-35. Digital Windowed Watchdog Reaction Control (RTIWWDRXNCTRL) Field Descriptions ...................... 620
17-36. Digital Windowed Watchdog Window Size Control (RTIWWDSIZECTRL) Field Descriptions ................. 621
17-37. RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE) Field Descriptions ...................... 622
17-38. RTI Compare 0 Clear Register (RTICMP0CLR) Field Descriptions ............................................... 623
17-39. RTI Compare 1 Clear Register (RTICMP1CLR) Field Descriptions ............................................... 623
17-40. RTI Compare 2 Clear Register (RTICMP2CLR) Field Descriptions ............................................... 624
17-41. RTI Compare 3 Clear Register (RTICMP3CLR) Field Descriptions ............................................... 624
18-1. CRC Modes in Which DMA Request and Counter Logic are Active or Inactive ................................. 633
18-2. Modes in Which Interrupt Condition Can Occur ...................................................................... 634
18-3. Interrupt Offset Mapping ................................................................................................. 637

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