Infineon Technologies TC1796 - Page 1450

TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-155 V2.0, 2007-07
MultiCAN, V2.0
TTCR Time Trigger Control Register 2C0
H
Page 22-169
TTCFGR Time Trigger Configuration Register 2C4
H
Page 22-173
TTSR Time Trigger Status Register 2C8
H
Page 22-175
TTFMR Time Trigger Flag Modification Register 2CC
H
Page 22-180
TTIRR Time Trigger Interrupt Request Register 2D0
H
Page 22-182
TTIER Time Trigger Interrupt Enable Register 2D4
H
Page 22-186
TTINPR Time Trigger Interrupt Node Pointer Register 2D8
H
Page 22-190
STSRL Scheduler Timing Status Register Low 2F0
H
Page 22-193
STSRH Scheduler Timing Status Register High 2F4
H
Page 22-194
SISR Scheduler Instruction Status Register 2F8
H
Page 22-195
STPTR0 Scheduler Start Pointer Node 0 Register 17FC
H
Page 22-192
Table 22-14 TTCAN Registers (cont’d)
Register
Short Name
Register Long Name Offset
Address
Description
see