IBCM IBCR
swap swap
1 02
17 1618
1 024 35
20 1921 17 1618
31
15
6
22
Host
Message
RAM
FlexRay
IBF
IBF
Sha-
dow
IBF = Input Buffer
Host
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Module Operation
1253
SPNU563A–March 2018
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FlexRay Module
26.2.12.2.1 Data Transfer from Input Buffer to Message RAM
To configure / update a message buffer in the message RAM, the host has to write the data to WRDSn
and the header to WRHS1…3. The specific action is selected by configuring the input buffer command
mask IBCM.
When the host writes the number of the target message buffer in the message RAM to IBCR.IBRH(6-0) in
the input buffer command request register IBCR, IBF host and IBF shadow are swapped (Figure 26-18).
Figure 26-18. Double Buffer Structure Input Buffer
Figure 26-19. Swapping of IBCM and IBCR Bits
With this write operation the IBCR.IBSYS bit in the input buffer command request register is set to 1. The
message handler then starts to transfer the contents of IBF shadow to the message buffer in the message
RAM selected by IBCR.IBRS(6-0).
While the message handler transfers the data from IBF shadow to the target message buffer in the
message RAM, the host may write the next message to IBF host. After the transfer between IBF shadow
and the message RAM has completed, the IBCR.IBSYS bit is set back to 0 and the next transfer to the
message RAM may be started by the host by writing the corresponding target message buffer number to
IBCR.IBRH(6-0) in the input buffer command request register.
If a write access to IBCR.IBRH(6-0) occurs while IBCR.IBSYS is 1, IBCR.IBSYH is set to 1. After
completion of the ongoing data transfer from IBF shadow to the message RAM, IBF host and IBF shadow
are swapped, IBCR.IBSYH is reset to 0, IBCR.IBSYS remains set to 1, and the next transfer to the
message RAM is started. In addition the message buffer numbers stored under IBCR.IBRH(6-0) and
IBCR.IBRS(6-0) and the command mask flags are also swapped.
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