FlexRay Module Registers
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SPNU563A–March 2018
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FlexRay Module
26.3.2.2.4 Status Interrupt Line Select (SILS)
The settings in the status interrupt line select register assign an interrupt generated by a specific status
interrupt flag to one of the two module interrupt lines (CC_int0 or CC_int1).
Figure 26-120 and Table 26-99 illustrate this register.
Figure 26-120. Status Interrupt Line Select Register (SILS) [offset_CC = 2Ch]
31 26 25 24 23 18 17 16
Reserved MTSBL WUPBL Reserved MTSAL WUPAL
R-0 R/W-1 R/W-1 R-0 R/W-1 R/W-1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDSL MBSIL SUCSL SWEL TOBCL TIBCL TI1L TI0L NMVCL RFFL RFNEL RXIL TXIL CYCSL CASL WSTL
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26-99. Status Interrupt Line Select Register (SILS) Field Descriptions
Bit Field Value Description
31-26 Reserved 0 Reads return 0. Writes have no effect.
25 MTSBL Media access test symbol channel B interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
24 WUPBL Wakeup pattern channel B interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
23-18 Reserved 0 Reads return 0. Writes have no effect.
17 MTSAL Media access test symbol channel A interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
16 WUPAL Wakeup pattern channel A interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
15 SDSL Start of Dynamic Segment Interrupt Line
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
14 MBSIL Message buffer status interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
13 SUCSL Startup completed Successfully interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
12 SWEL Stop watch event interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
11 TOBCL Transfer output buffer completed interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
10 TIBCL Transfer input buffer completed interrupt line.
0 Interrupt is assigned to interrupt line CC_int0.
1 Interrupt is assigned to interrupt line CC_int1.
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